91427e6d90
There is a performance issue when the number of VSIs are not multiple
of 8. This is caused due to the max children limitation per node(8) in
9 layer topology. The BW credits are shared evenly among the children
by default. Assume one node has 8 children and the other has 1.
The parent of these nodes share the BW credit equally among them.
Apparently this causes a problem for the first node which has 8 children.
The 9th VM get more BW credits than the first 8 VMs.
Example:
1) With 8 VM's:
for x in 0 1 2 3 4 5 6 7;
do taskset -c ${x} netperf -P0 -H 172.68.169.125 & sleep .1 ; done
tx_queue_0_packets: 23283027
tx_queue_1_packets: 23292289
tx_queue_2_packets: 23276136
tx_queue_3_packets: 23279828
tx_queue_4_packets: 23279828
tx_queue_5_packets: 23279333
tx_queue_6_packets: 23277745
tx_queue_7_packets: 23279950
tx_queue_8_packets: 0
2) With 9 VM's:
for x in 0 1 2 3 4 5 6 7 8;
do taskset -c ${x} netperf -P0 -H 172.68.169.125 & sleep .1 ; done
tx_queue_0_packets: 24163396
tx_queue_1_packets: 24164623
tx_queue_2_packets: 24163188
tx_queue_3_packets: 24163701
tx_queue_4_packets: 24163683
tx_queue_5_packets: 24164668
tx_queue_6_packets: 23327200
tx_queue_7_packets: 24163853
tx_queue_8_packets: 91101417
So on average queue 8 statistics show that 3.7 times more packets were
send there than to the other queues.
The FW starting with version 3.20, has increased the max number of
children per node by reducing the number of layers from 9 to 5. Reflect
this on driver side.
Signed-off-by: Raj Victor <victor.raj@intel.com>
Co-developed-by: Michal Wilczynski <michal.wilczynski@intel.com>
Signed-off-by: Michal Wilczynski <michal.wilczynski@intel.com>
Co-developed-by: Mateusz Polchlopek <mateusz.polchlopek@intel.com>
Signed-off-by: Mateusz Polchlopek <mateusz.polchlopek@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
179 lines
6.4 KiB
C
179 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, Intel Corporation. */
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#ifndef _ICE_SCHED_H_
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#define _ICE_SCHED_H_
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#include "ice_common.h"
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/**
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* DOC: ice_sched.h
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*
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* This header file stores everything that is needed for broadly understood
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* scheduler. It consists of defines related to layers, structures related to
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* aggregator, functions declarations and others.
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*/
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#define ICE_SCHED_5_LAYERS 5
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#define ICE_SCHED_9_LAYERS 9
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#define SCHED_NODE_NAME_MAX_LEN 32
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#define ICE_QGRP_LAYER_OFFSET 2
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#define ICE_VSI_LAYER_OFFSET 4
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#define ICE_AGG_LAYER_OFFSET 6
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#define ICE_SCHED_INVAL_LAYER_NUM 0xFF
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/* Burst size is a 12 bits register that is configured while creating the RL
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* profile(s). MSB is a granularity bit and tells the granularity type
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* 0 - LSB bits are in 64 bytes granularity
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* 1 - LSB bits are in 1K bytes granularity
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*/
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#define ICE_64_BYTE_GRANULARITY 0
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#define ICE_KBYTE_GRANULARITY BIT(11)
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#define ICE_MIN_BURST_SIZE_ALLOWED 64 /* In Bytes */
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#define ICE_MAX_BURST_SIZE_ALLOWED \
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((BIT(11) - 1) * 1024) /* In Bytes */
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#define ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY \
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((BIT(11) - 1) * 64) /* In Bytes */
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#define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY ICE_MAX_BURST_SIZE_ALLOWED
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#define ICE_RL_PROF_ACCURACY_BYTES 128
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#define ICE_RL_PROF_MULTIPLIER 10000
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#define ICE_RL_PROF_TS_MULTIPLIER 32
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#define ICE_RL_PROF_FRACTION 512
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#define ICE_PSM_CLK_367MHZ_IN_HZ 367647059
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#define ICE_PSM_CLK_416MHZ_IN_HZ 416666667
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#define ICE_PSM_CLK_446MHZ_IN_HZ 446428571
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#define ICE_PSM_CLK_390MHZ_IN_HZ 390625000
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/* BW rate limit profile parameters list entry along
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* with bandwidth maintained per layer in port info
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*/
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struct ice_aqc_rl_profile_info {
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struct ice_aqc_rl_profile_elem profile;
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struct list_head list_entry;
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u32 bw; /* requested */
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u16 prof_id_ref; /* profile ID to node association ref count */
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};
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struct ice_sched_agg_vsi_info {
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struct list_head list_entry;
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DECLARE_BITMAP(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
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u16 vsi_handle;
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/* save aggregator VSI TC bitmap */
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DECLARE_BITMAP(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
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};
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struct ice_sched_agg_info {
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struct list_head agg_vsi_list;
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struct list_head list_entry;
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DECLARE_BITMAP(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
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u32 agg_id;
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enum ice_agg_type agg_type;
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/* bw_t_info saves aggregator BW information */
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struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
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/* save aggregator TC bitmap */
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DECLARE_BITMAP(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
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};
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/* FW AQ command calls */
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int
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ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,
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struct ice_aqc_txsched_elem_data *buf, u16 buf_size,
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u16 *elems_ret, struct ice_sq_cd *cd);
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int
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ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node,
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enum ice_rl_type rl_type, u32 bw);
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int
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ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node,
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enum ice_rl_type rl_type, u32 bw, u8 layer_num);
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int
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ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node,
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struct ice_sched_node *parent, u8 layer, u16 num_nodes,
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u16 *num_nodes_added, u32 *first_node_teid,
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struct ice_sched_node **prealloc_node);
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int
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ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent,
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u16 num_items, u32 *list);
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int ice_sched_set_node_priority(struct ice_port_info *pi, struct ice_sched_node *node,
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u16 priority);
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int ice_sched_set_node_weight(struct ice_port_info *pi, struct ice_sched_node *node, u16 weight);
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int ice_sched_init_port(struct ice_port_info *pi);
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int ice_sched_query_res_alloc(struct ice_hw *hw);
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void ice_sched_get_psm_clk_freq(struct ice_hw *hw);
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void ice_sched_clear_port(struct ice_port_info *pi);
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void ice_sched_cleanup_all(struct ice_hw *hw);
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void ice_sched_clear_agg(struct ice_hw *hw);
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struct ice_sched_node *
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ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid);
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int
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ice_sched_add_node(struct ice_port_info *pi, u8 layer,
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struct ice_aqc_txsched_elem_data *info,
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struct ice_sched_node *prealloc_node);
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void
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ice_sched_update_parent(struct ice_sched_node *new_parent,
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struct ice_sched_node *node);
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void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node);
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struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc);
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struct ice_sched_node *
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ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
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u8 owner);
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int
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ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs,
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u8 owner, bool enable);
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int ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle);
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int ice_rm_vsi_rdma_cfg(struct ice_port_info *pi, u16 vsi_handle);
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/* Tx scheduler rate limiter functions */
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int
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ice_cfg_agg(struct ice_port_info *pi, u32 agg_id,
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enum ice_agg_type agg_type, u8 tc_bitmap);
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int
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ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle,
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u8 tc_bitmap);
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int
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ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
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u16 q_handle, enum ice_rl_type rl_type, u32 bw);
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int
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ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
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u16 q_handle, enum ice_rl_type rl_type);
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int
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ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
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enum ice_rl_type rl_type, u32 bw);
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int
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ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
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enum ice_rl_type rl_type);
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int ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
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int
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ice_sched_suspend_resume_elems(struct ice_hw *hw, u8 num_nodes, u32 *node_teids,
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bool suspend);
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struct ice_sched_node *
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ice_sched_get_agg_node(struct ice_port_info *pi, struct ice_sched_node *tc_node,
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u32 agg_id);
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u8 ice_sched_get_agg_layer(struct ice_hw *hw);
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u8 ice_sched_get_vsi_layer(struct ice_hw *hw);
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struct ice_sched_node *
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ice_sched_get_free_vsi_parent(struct ice_hw *hw, struct ice_sched_node *node,
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u16 *num_nodes);
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int
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ice_sched_add_nodes_to_layer(struct ice_port_info *pi,
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struct ice_sched_node *tc_node,
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struct ice_sched_node *parent, u8 layer,
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u16 num_nodes, u32 *first_node_teid,
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u16 *num_nodes_added);
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void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw);
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void ice_sched_replay_agg(struct ice_hw *hw);
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int ice_aq_move_sched_elems(struct ice_hw *hw, struct ice_aqc_move_elem *buf,
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u16 buf_size, u16 *grps_movd);
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int ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle);
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int ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);
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#endif /* _ICE_SCHED_H_ */
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