7c352a4d01
Currently we do reset for each RDDM event from MHI, however there are cases, see below log, that we get two or more consecutive events, and it is pointless to do reset for the subsequent ones. What's more, it makes reset process more likely to fail. [ 1502.115876] ath11k_pci 0000:04:00.0: boot notify status reason MHI_CB_EE_RDDM [ 1502.115884] ath11k_pci 0000:04:00.0: firmware crashed: MHI_CB_EE_RDDM [ 1502.224041] ath11k_pci 0000:04:00.0: boot notify status reason MHI_CB_EE_RDDM [ 1502.224050] ath11k_pci 0000:04:00.0: firmware crashed: MHI_CB_EE_RDDM Add a check to avoid reset again and again. This is done by tracking previous MHI status: if we receive a new RDDM event while the previous one is also the same, we treat it as duplicate and ignore it, because normally we should receive a MHI_CB_EE_MISSION_MODE event between them. Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3.6510.23 Signed-off-by: Baochen Qiang <quic_bqiang@quicinc.com> Acked-by: Jeff Johnson <quic_jjohnson@quicinc.com> Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com> Link: https://msgid.link/20240111071406.14053-1-quic_bqiang@quicinc.com
85 lines
2.4 KiB
C
85 lines
2.4 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
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/*
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* Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2022,2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _ATH11K_PCI_H
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#define _ATH11K_PCI_H
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#include <linux/mhi.h>
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#include "core.h"
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#define PCIE_SOC_GLOBAL_RESET 0x3008
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#define PCIE_SOC_GLOBAL_RESET_V 1
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#define WLAON_WARM_SW_ENTRY 0x1f80504
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#define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c
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#define PCIE_Q6_COOKIE_ADDR 0x01f80500
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#define PCIE_Q6_COOKIE_DATA 0xc0000000
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/* register to wake the UMAC from power collapse */
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#define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040
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/* register used for handshake mechanism to validate UMAC is awake */
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#define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004
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#define PCIE_PCIE_PARF_LTSSM 0x1e081b0
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#define PARM_LTSSM_VALUE 0x111
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#define GCC_GCC_PCIE_HOT_RST 0x1e402bc
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#define GCC_GCC_PCIE_HOT_RST_VAL 0x10
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#define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228
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#define PCIE_SMLH_REQ_RST_LINK_DOWN 0x2
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#define PCIE_INT_CLEAR_ALL 0xffffffff
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#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(x) \
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(ab->hw_params.regs->pcie_qserdes_sysclk_en_sel)
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#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL 0x10
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#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK 0xffffffff
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#define PCIE_PCS_OSC_DTCT_CONFIG1_REG(x) \
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(ab->hw_params.regs->pcie_pcs_osc_dtct_config_base)
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#define PCIE_PCS_OSC_DTCT_CONFIG1_VAL 0x02
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#define PCIE_PCS_OSC_DTCT_CONFIG2_REG(x) \
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(ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0x4)
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#define PCIE_PCS_OSC_DTCT_CONFIG2_VAL 0x52
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#define PCIE_PCS_OSC_DTCT_CONFIG4_REG(x) \
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(ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0xc)
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#define PCIE_PCS_OSC_DTCT_CONFIG4_VAL 0xff
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#define PCIE_PCS_OSC_DTCT_CONFIG_MSK 0x000000ff
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#define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c
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#define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4
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enum ath11k_pci_flags {
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ATH11K_PCI_ASPM_RESTORE,
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};
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struct ath11k_pci {
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struct pci_dev *pdev;
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struct ath11k_base *ab;
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u16 dev_id;
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char amss_path[100];
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struct mhi_controller *mhi_ctrl;
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const struct ath11k_msi_config *msi_config;
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enum mhi_callback mhi_pre_cb;
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u32 register_window;
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/* protects register_window above */
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spinlock_t window_lock;
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/* enum ath11k_pci_flags */
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unsigned long flags;
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u16 link_ctl;
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u64 dma_mask;
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};
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static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab)
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{
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return (struct ath11k_pci *)ab->drv_priv;
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}
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int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector);
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#endif
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