886c5be0b1
As the selftest enclave is *not* intended for production, simplify the code by not initializing CPU configuration registers as expected by the ABI on enclave entry or cleansing caller-save registers on enclave exit. Signed-off-by: Jo Van Bulck <jo.vanbulck@cs.kuleuven.be> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Reviewed-by: Jarkko Sakkinen <jarkko@kernel.org> Link: https://lore.kernel.org/all/da0cfb1e-e347-f7f2-ac72-aec0ee0d867d@intel.com/ Link: https://lore.kernel.org/all/20231005153854.25566-14-jo.vanbulck%40cs.kuleuven.be
92 lines
2.1 KiB
ArmAsm
92 lines
2.1 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright(c) 2016-20 Intel Corporation.
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*/
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.macro ENCLU
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.byte 0x0f, 0x01, 0xd7
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.endm
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.section ".tcs", "aw"
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.balign 4096
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.fill 1, 8, 0 # STATE (set by CPU)
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.fill 1, 8, 0 # FLAGS
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.quad encl_ssa_tcs1 # OSSA
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.fill 1, 4, 0 # CSSA (set by CPU)
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.fill 1, 4, 1 # NSSA
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.quad encl_entry # OENTRY
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.fill 1, 8, 0 # AEP (set by EENTER and ERESUME)
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.fill 1, 8, 0 # OFSBASE
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.fill 1, 8, 0 # OGSBASE
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.fill 1, 4, 0xFFFFFFFF # FSLIMIT
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.fill 1, 4, 0xFFFFFFFF # GSLIMIT
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.fill 4024, 1, 0 # Reserved
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# TCS2
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.fill 1, 8, 0 # STATE (set by CPU)
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.fill 1, 8, 0 # FLAGS
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.quad encl_ssa_tcs2 # OSSA
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.fill 1, 4, 0 # CSSA (set by CPU)
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.fill 1, 4, 1 # NSSA
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.quad encl_entry # OENTRY
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.fill 1, 8, 0 # AEP (set by EENTER and ERESUME)
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.fill 1, 8, 0 # OFSBASE
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.fill 1, 8, 0 # OGSBASE
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.fill 1, 4, 0xFFFFFFFF # FSLIMIT
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.fill 1, 4, 0xFFFFFFFF # GSLIMIT
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.fill 4024, 1, 0 # Reserved
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.text
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encl_entry:
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# RBX contains the base address for TCS, which is the first address
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# inside the enclave for TCS #1 and one page into the enclave for
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# TCS #2. First make it relative by substracting __encl_base and
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# then add the address of encl_stack to get the address for the stack.
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lea __encl_base(%rip), %rax
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sub %rax, %rbx
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lea encl_stack(%rip), %rax
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add %rbx, %rax
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jmp encl_entry_core
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encl_dyn_entry:
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# Entry point for dynamically created TCS page expected to follow
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# its stack directly.
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lea -1(%rbx), %rax
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encl_entry_core:
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xchg %rsp, %rax
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push %rax
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push %rcx # push the address after EENTER
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# NOTE: as the selftest enclave is *not* intended for production,
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# simplify the code by not initializing ABI registers on entry or
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# cleansing caller-save registers on exit.
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call encl_body
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# Prepare EEXIT target by popping the address of the instruction after
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# EENTER to RBX.
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pop %rbx
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# Restore the caller stack.
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pop %rax
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mov %rax, %rsp
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# EEXIT
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mov $4, %rax
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enclu
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.section ".data", "aw"
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encl_ssa_tcs1:
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.space 4096
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encl_ssa_tcs2:
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.space 4096
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.balign 4096
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# Stack of TCS #1
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.space 4096
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encl_stack:
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.balign 4096
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# Stack of TCS #2
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.space 4096
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