553f973a0d
This patch updates the 'regs2' interface for MMIO registers to add a new IOCTL command for a 'v2' state data that includes the XCC ID. This patch then updates amdgpu_gfx_select_se_sh() and amdgpu_gfx_select_me_pipe_q() (and the implementations in the gfx drivers) to support an additional parameter. This patch then creates a new debugfs interface "gprwave" which is a merge of shader GPR and wave status access. This new inteface uses an IOCTL to select banks as well as XCC identity. (v2) Fix missing xcc_id in wave_ind function (v3) Fix pm runtime calls and mutex locking (v4) Fix bad label Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
85 lines
2.6 KiB
C
85 lines
2.6 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/ioctl.h>
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/*
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* MMIO debugfs IOCTL structure
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*/
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struct amdgpu_debugfs_regs2_iocdata {
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__u32 use_srbm, use_grbm, pg_lock;
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struct {
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__u32 se, sh, instance;
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} grbm;
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struct {
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__u32 me, pipe, queue, vmid;
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} srbm;
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};
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struct amdgpu_debugfs_regs2_iocdata_v2 {
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__u32 use_srbm, use_grbm, pg_lock;
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struct {
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__u32 se, sh, instance;
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} grbm;
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struct {
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__u32 me, pipe, queue, vmid;
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} srbm;
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u32 xcc_id;
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};
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struct amdgpu_debugfs_gprwave_iocdata {
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u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id;
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struct {
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u32 thread, vpgr_or_sgpr;
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} gpr;
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};
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/*
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* MMIO debugfs state data (per file* handle)
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*/
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struct amdgpu_debugfs_regs2_data {
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struct amdgpu_device *adev;
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struct mutex lock;
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struct amdgpu_debugfs_regs2_iocdata_v2 id;
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};
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struct amdgpu_debugfs_gprwave_data {
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struct amdgpu_device *adev;
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struct mutex lock;
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struct amdgpu_debugfs_gprwave_iocdata id;
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};
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enum AMDGPU_DEBUGFS_REGS2_CMDS {
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AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE=0,
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AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE_V2,
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};
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enum AMDGPU_DEBUGFS_GPRWAVE_CMDS {
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AMDGPU_DEBUGFS_GPRWAVE_CMD_SET_STATE=0,
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};
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//reg2 interface
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#define AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE _IOWR(0x20, AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE, struct amdgpu_debugfs_regs2_iocdata)
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#define AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE_V2 _IOWR(0x20, AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE_V2, struct amdgpu_debugfs_regs2_iocdata_v2)
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//gprwave interface
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#define AMDGPU_DEBUGFS_GPRWAVE_IOC_SET_STATE _IOWR(0x20, AMDGPU_DEBUGFS_GPRWAVE_CMD_SET_STATE, struct amdgpu_debugfs_gprwave_iocdata)
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