379b4f7645
Annotate the external MDIO2 node and describe the 10GBASER PHY found on the LS1088ARDB board and add a phy-handle for DPMAC2 to link it. Also, add the internal PCS MDIO node for the internal MDIO buses found on the LS1088A SoC along with its internal PCS PHY and link the corresponding DPMAC to the PCS through the pcs-handle. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
244 lines
3.6 KiB
Text
244 lines
3.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for NXP LS1088A RDB Board.
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*
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* Copyright 2017 NXP
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*
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* Harninder Rai <harninder.rai@nxp.com>
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*
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*/
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/dts-v1/;
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#include "fsl-ls1088a.dtsi"
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/ {
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model = "LS1088A RDB Board";
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compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
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};
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&dpmac2 {
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phy-handle = <&mdio2_aquantia_phy>;
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phy-connection-type = "10gbase-r";
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pcs-handle = <&pcs2>;
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};
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&dpmac3 {
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phy-handle = <&mdio1_phy5>;
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phy-connection-type = "qsgmii";
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managed = "in-band-status";
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pcs-handle = <&pcs3_0>;
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};
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&dpmac4 {
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phy-handle = <&mdio1_phy6>;
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phy-connection-type = "qsgmii";
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managed = "in-band-status";
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pcs-handle = <&pcs3_1>;
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};
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&dpmac5 {
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phy-handle = <&mdio1_phy7>;
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phy-connection-type = "qsgmii";
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managed = "in-band-status";
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pcs-handle = <&pcs3_2>;
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};
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&dpmac6 {
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phy-handle = <&mdio1_phy8>;
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phy-connection-type = "qsgmii";
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managed = "in-band-status";
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pcs-handle = <&pcs3_3>;
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};
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&dpmac7 {
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phy-handle = <&mdio1_phy1>;
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phy-connection-type = "qsgmii";
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managed = "in-band-status";
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pcs-handle = <&pcs7_0>;
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};
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&dpmac8 {
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phy-handle = <&mdio1_phy2>;
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phy-connection-type = "qsgmii";
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managed = "in-band-status";
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pcs-handle = <&pcs7_1>;
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};
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&dpmac9 {
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phy-handle = <&mdio1_phy3>;
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phy-connection-type = "qsgmii";
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managed = "in-band-status";
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pcs-handle = <&pcs7_2>;
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};
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&dpmac10 {
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phy-handle = <&mdio1_phy4>;
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phy-connection-type = "qsgmii";
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managed = "in-band-status";
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pcs-handle = <&pcs7_3>;
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};
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&emdio1 {
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status = "okay";
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mdio1_phy5: ethernet-phy@c {
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reg = <0xc>;
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};
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mdio1_phy6: ethernet-phy@d {
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reg = <0xd>;
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};
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mdio1_phy7: ethernet-phy@e {
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reg = <0xe>;
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};
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mdio1_phy8: ethernet-phy@f {
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reg = <0xf>;
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};
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mdio1_phy1: ethernet-phy@1c {
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reg = <0x1c>;
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};
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mdio1_phy2: ethernet-phy@1d {
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reg = <0x1d>;
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};
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mdio1_phy3: ethernet-phy@1e {
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reg = <0x1e>;
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};
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mdio1_phy4: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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&emdio2 {
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status = "okay";
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mdio2_aquantia_phy: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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};
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&i2c0 {
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status = "okay";
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i2c-switch@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
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ina220@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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temp-sensor@4c {
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compatible = "adi,adt7461a";
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reg = <0x4c>;
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};
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rtc@51 {
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compatible = "nxp,pcf2129";
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reg = <0x51>;
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/* IRQ10_B */
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interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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};
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&ifc {
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ranges = <0 0 0x5 0x30000000 0x00010000
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2 0 0x5 0x20000000 0x00010000>;
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status = "okay";
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nand@0,0 {
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compatible = "fsl,ifc-nand";
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reg = <0x0 0x0 0x10000>;
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};
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fpga: board-control@2,0 {
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compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
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reg = <0x2 0x0 0x0000100>;
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};
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};
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&duart0 {
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status = "okay";
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};
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&duart1 {
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status = "okay";
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};
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&esdhc {
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mmc-hs200-1_8v;
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status = "okay";
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};
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&pcs_mdio2 {
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status = "okay";
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};
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&pcs_mdio3 {
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status = "okay";
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};
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&pcs_mdio7 {
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status = "okay";
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};
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&qspi {
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status = "okay";
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s25fs512s0: flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <1>;
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reg = <0>;
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};
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s25fs512s1: flash@1 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <1>;
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reg = <1>;
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};
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};
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&sata {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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dr_mode = "otg";
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status = "okay";
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};
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