e2ae634014
We have a handful of new kernel features for 5.11:
* Support for the contiguous memory allocator.
* Support for IRQ Time Accounting
* Support for stack tracing
* Support for strict /dev/mem
* Support for kernel section protection
I'm being a bit conservative on the cutoff for this round due to the
timing, so this is all the new development I'm going to take for this
cycle (even if some of it probably normally would have been OK). There
are, however, some fixes on the list that I will likely be sending along
either later this week or early next week.
There is one issue in here: one of my test configurations
(PREEMPT{,_DEBUG}=y) fails to boot on QEMU 5.0.0 (from April) as of the
.text.init alignment patch. With any luck we'll sort out the issue, but
given how many bugs get fixed all over the place and how unrelated those
features seem my guess is that we're just running into something that's
been lurking for a while and has already been fixed in the newer QEMU
(though I wouldn't be surprised if it's one of these implicit
assumptions we have in the boot flow). If it was hardware I'd be
strongly inclined to look more closely, but given that users can upgrade
their simulators I'm less worried about it.
There are two merge conflicts, both in build files. They're both a bit
clunky: arch/riscv/Kconfig is out of order (I have a script that's
supposed to keep them in order, I'll fix it) and lib/Makefile is out of
order (though GENERIC_LIB here doesn't mean quite what it does above).
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Merge tag 'riscv-for-linus-5.11-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
"We have a handful of new kernel features for 5.11:
- Support for the contiguous memory allocator.
- Support for IRQ Time Accounting
- Support for stack tracing
- Support for strict /dev/mem
- Support for kernel section protection
I'm being a bit conservative on the cutoff for this round due to the
timing, so this is all the new development I'm going to take for this
cycle (even if some of it probably normally would have been OK). There
are, however, some fixes on the list that I will likely be sending
along either later this week or early next week.
There is one issue in here: one of my test configurations
(PREEMPT{,_DEBUG}=y) fails to boot on QEMU 5.0.0 (from April) as of
the .text.init alignment patch.
With any luck we'll sort out the issue, but given how many bugs get
fixed all over the place and how unrelated those features seem my
guess is that we're just running into something that's been lurking
for a while and has already been fixed in the newer QEMU (though I
wouldn't be surprised if it's one of these implicit assumptions we
have in the boot flow). If it was hardware I'd be strongly inclined to
look more closely, but given that users can upgrade their simulators
I'm less worried about it"
* tag 'riscv-for-linus-5.11-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
arm64: Use the generic devmem_is_allowed()
arm: Use the generic devmem_is_allowed()
RISC-V: Use the new generic devmem_is_allowed()
lib: Add a generic version of devmem_is_allowed()
riscv: Fixed kernel test robot warning
riscv: kernel: Drop unused clean rule
riscv: provide memmove implementation
RISC-V: Move dynamic relocation section under __init
RISC-V: Protect all kernel sections including init early
RISC-V: Align the .init.text section
RISC-V: Initialize SBI early
riscv: Enable ARCH_STACKWALK
riscv: Make stack walk callback consistent with generic code
riscv: Cleanup stacktrace
riscv: Add HAVE_IRQ_TIME_ACCOUNTING
riscv: Enable CMA support
riscv: Ignore Image.* and loader.bin
riscv: Clean up boot dir
riscv: Fix compressed Image formats build
RISC-V: Add kernel image sections to the resource tree
45 lines
1.5 KiB
C
45 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2019 SiFive
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*/
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#ifndef _ASM_RISCV_SET_MEMORY_H
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#define _ASM_RISCV_SET_MEMORY_H
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#ifndef __ASSEMBLY__
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/*
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* Functions to change memory attributes.
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*/
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#ifdef CONFIG_MMU
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int set_memory_ro(unsigned long addr, int numpages);
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int set_memory_rw(unsigned long addr, int numpages);
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int set_memory_x(unsigned long addr, int numpages);
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int set_memory_nx(unsigned long addr, int numpages);
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int set_memory_rw_nx(unsigned long addr, int numpages);
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void protect_kernel_text_data(void);
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#else
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static inline int set_memory_ro(unsigned long addr, int numpages) { return 0; }
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static inline int set_memory_rw(unsigned long addr, int numpages) { return 0; }
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static inline int set_memory_x(unsigned long addr, int numpages) { return 0; }
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static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; }
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static inline void protect_kernel_text_data(void) {};
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static inline int set_memory_rw_nx(unsigned long addr, int numpages) { return 0; }
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#endif
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int set_direct_map_invalid_noflush(struct page *page);
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int set_direct_map_default_noflush(struct page *page);
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bool kernel_page_present(struct page *page);
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#endif /* __ASSEMBLY__ */
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#ifdef CONFIG_ARCH_HAS_STRICT_KERNEL_RWX
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#ifdef CONFIG_64BIT
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#define SECTION_ALIGN (1 << 21)
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#else
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#define SECTION_ALIGN (1 << 22)
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#endif
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#else /* !CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
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#define SECTION_ALIGN L1_CACHE_BYTES
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#endif /* CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
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#endif /* _ASM_RISCV_SET_MEMORY_H */
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