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linux/drivers/gpu/drm/amd/display/dc/dcn20
Alex Deucher 88d5cb2517 drm/amdgpu/display: drop DCN support for aarch64
From Ard:

"Simply disabling -mgeneral-regs-only left and right is risky, given that
the standard AArch64 ABI permits the use of FP/SIMD registers anywhere,
and GCC is known to use SIMD registers for spilling, and may invent
other uses of the FP/SIMD register file that have nothing to do with the
floating point code in question. Note that putting kernel_neon_begin()
and kernel_neon_end() around the code that does use FP is not sufficient
here, the problem is in all the other code that may be emitted with
references to SIMD registers in it.

So the only way to do this properly is to put all floating point code in
a separate compilation unit, and only compile that unit with
-mgeneral-regs-only."

Disable support until the code can be properly refactored to support this
properly on aarch64.

Acked-by: Will Deacon <will@kernel.org>
Reported-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-05 11:35:53 -05:00
..
dcn20_dccg.c drm/amd/display: DPP DTO isn't update properly. 2020-03-19 00:03:04 -04:00
dcn20_dccg.h drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3) 2020-11-04 17:11:37 -05:00
dcn20_dpp.c drm/amd/display: correct alpha_en programming for new pixel format 2020-07-01 01:59:19 -04:00
dcn20_dpp.h drm/amd/display: Add DSCL memory low power support 2020-12-01 16:03:40 -05:00
dcn20_dpp_cm.c drm/amd/display: Indirect reg read macro with shift and mask 2020-01-16 14:13:53 -05:00
dcn20_dsc.c drm/amd/display: Rename bytes_pp to the correct bits_pp 2020-07-27 16:23:21 -04:00
dcn20_dsc.h drm/amd/display: Add DSC_DBG_EN shift/mask for dcn3 2020-08-17 14:09:27 -04:00
dcn20_dwb.c drm/amd/display: [backport] dwb dm + efc support 2019-06-22 09:34:11 -05:00
dcn20_dwb.h drm/amd/display: Add DCN2 DWB 2019-06-21 18:59:35 -05:00
dcn20_dwb_scl.c drm/amd/display: Remove set but not used variables 'h_ratio_chroma', 'v_ratio_chroma' 2019-10-07 15:10:43 -05:00
dcn20_hubbub.c drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3) 2020-11-04 17:11:37 -05:00
dcn20_hubbub.h drm/amd/display: correct rn NUM_VMID 2020-05-21 12:48:43 -04:00
dcn20_hubp.c drm/amd/display: Interfaces for hubp blank and soft reset 2020-12-23 15:01:24 -05:00
dcn20_hubp.h drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3) 2020-11-04 17:11:37 -05:00
dcn20_hwseq.c drm/amd/display: Multi-display underflow observed 2020-12-23 15:02:18 -05:00
dcn20_hwseq.h drm/amd/display: Blank HUBP during pixel data blank for DCN30 v2 2020-11-02 15:31:30 -05:00
dcn20_init.c drm/amd/display: Blank HUBP during pixel data blank for DCN30 v2 2020-11-02 15:31:30 -05:00
dcn20_init.h drm/amd/display: cleanup of function pointer tables 2019-11-19 10:12:53 -05:00
dcn20_link_encoder.c drm/amd/display: Read VBIOS Golden Settings Tbl 2020-08-04 17:29:27 -04:00
dcn20_link_encoder.h drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3) 2020-11-04 17:11:37 -05:00
dcn20_mmhubbub.c drm/amd/display: Add DCN2 MMHUBBUB 2019-06-21 18:59:34 -05:00
dcn20_mmhubbub.h drm/amd/display: Update register defines 2020-02-11 11:50:18 -05:00
dcn20_mpc.c drm/amd/display: add getter routine to retrieve mpcc mux 2020-12-23 15:02:55 -05:00
dcn20_mpc.h drm/amd/display: Use cursor locking to prevent flip delays 2020-04-28 16:19:56 -04:00
dcn20_opp.c drm/amd/display: Raise DPG height during timing synchronization 2020-10-26 13:29:21 -04:00
dcn20_opp.h drm/amd/display: Raise DPG height during timing synchronization 2020-10-26 13:29:21 -04:00
dcn20_optc.c drm/amd/display: Fix OPTC_DATA_FORMAT programming 2020-10-05 15:16:57 -04:00
dcn20_optc.h drm/amd/display: add optc get crc support for timings with ODM/DSC 2020-04-22 18:11:47 -04:00
dcn20_resource.c drm/amd/display: Acquire DSC during split stream for ODM only if top_pipe 2020-12-23 15:02:24 -05:00
dcn20_resource.h drm/amd/display: Prevent freesync power optimization during validation 2020-11-10 14:24:48 -05:00
dcn20_stream_encoder.c drm/amd/display: Rename set_mst_bandwidth to align with DP spec 2020-09-15 17:52:41 -04:00
dcn20_stream_encoder.h drm/amd/display: Add missing DP_SEC register definitions and masks 2020-12-15 11:33:33 -05:00
dcn20_vmid.c drm/amd/display: Poll for GPUVM context ready (v2) 2019-07-18 14:18:09 -05:00
dcn20_vmid.h drm/amd/display: Update register defines 2020-02-11 11:50:18 -05:00
Makefile drm/amdgpu/display: drop DCN support for aarch64 2021-01-05 11:35:53 -05:00