88d5cb2517
From Ard: "Simply disabling -mgeneral-regs-only left and right is risky, given that the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, and GCC is known to use SIMD registers for spilling, and may invent other uses of the FP/SIMD register file that have nothing to do with the floating point code in question. Note that putting kernel_neon_begin() and kernel_neon_end() around the code that does use FP is not sufficient here, the problem is in all the other code that may be emitted with references to SIMD registers in it. So the only way to do this properly is to put all floating point code in a separate compilation unit, and only compile that unit with -mgeneral-regs-only." Disable support until the code can be properly refactored to support this properly on aarch64. Acked-by: Will Deacon <will@kernel.org> Reported-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
37 lines
824 B
Makefile
37 lines
824 B
Makefile
# SPDX-License-Identifier: MIT
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#
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# Makefile for the 'dsc' sub-component of DAL.
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ifdef CONFIG_X86
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dsc_ccflags := -mhard-float -msse
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endif
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ifdef CONFIG_PPC64
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dsc_ccflags := -mhard-float -maltivec
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endif
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ifdef CONFIG_CC_IS_GCC
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ifeq ($(call cc-ifversion, -lt, 0701, y), y)
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IS_OLD_GCC = 1
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endif
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endif
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ifdef CONFIG_X86
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ifdef IS_OLD_GCC
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# Stack alignment mismatch, proceed with caution.
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# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
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# (8B stack alignment).
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dsc_ccflags += -mpreferred-stack-boundary=4
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else
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dsc_ccflags += -msse2
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endif
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endif
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CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_ccflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_rcflags)
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DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o
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AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
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AMD_DISPLAY_FILES += $(AMD_DAL_DSC)
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