0d0d498265
There are extra registers that need to be programmed to make the level 2 cache work on GP10B, such as the stream ID register that is used when an SMMU is used to translate memory addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
9 lines
302 B
Makefile
9 lines
302 B
Makefile
# SPDX-License-Identifier: MIT
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nvkm-y += nvkm/subdev/ltc/base.o
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nvkm-y += nvkm/subdev/ltc/gf100.o
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nvkm-y += nvkm/subdev/ltc/gk104.o
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nvkm-y += nvkm/subdev/ltc/gm107.o
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nvkm-y += nvkm/subdev/ltc/gm200.o
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nvkm-y += nvkm/subdev/ltc/gp100.o
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nvkm-y += nvkm/subdev/ltc/gp102.o
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nvkm-y += nvkm/subdev/ltc/gp10b.o
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