176ada03e3
Turing introduced a new simplified page kind scheme, reducing the number of possible page kinds from 256 to 16. It also is the first NVIDIA GPU in which the highest possible page kind value is not reserved as an "invalid" page kind. To address this, the invalid page kind is made an explicit property of the MMU HAL, and a new table of page kinds is added to the tu102 MMU HAL. One hardware change not addressed here is that 0x00 is technically no longer a supported page kind, and pitch surfaces are instead intended to share the block-linear generic page kind 0x06. However, because that will be a rather invasive change to nouveau and 0x00 still works fine in practice on Turing hardware, addressing this new behavior is deferred. Signed-off-by: James Jones <jajones@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
77 lines
2.8 KiB
C
77 lines
2.8 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "mem.h"
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#include "vmm.h"
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#include <nvif/class.h>
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const u8 *
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nv50_mmu_kind(struct nvkm_mmu *base, int *count, u8 *invalid)
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{
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/* 0x01: no bank swizzle
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* 0x02: bank swizzled
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* 0x7f: invalid
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*
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* 0x01/0x02 are values understood by the VRAM allocator,
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* and are required to avoid mixing the two types within
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* a certain range.
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*/
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static const u8
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kind[128] = {
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0x01, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, /* 0x00 */
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0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
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0x01, 0x01, 0x01, 0x01, 0x7f, 0x7f, 0x7f, 0x7f, /* 0x10 */
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0x02, 0x02, 0x02, 0x02, 0x7f, 0x7f, 0x7f, 0x7f,
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0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x7f, /* 0x20 */
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0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x7f,
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0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, /* 0x30 */
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0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
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0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, /* 0x40 */
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0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x7f, 0x7f,
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0x7f, 0x7f, 0x7f, 0x7f, 0x01, 0x01, 0x01, 0x7f, /* 0x50 */
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0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
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0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x7f, /* 0x60 */
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0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02,
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0x01, 0x7f, 0x02, 0x7f, 0x01, 0x7f, 0x02, 0x7f, /* 0x70 */
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0x01, 0x01, 0x02, 0x02, 0x01, 0x01, 0x7f, 0x7f
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};
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*count = ARRAY_SIZE(kind);
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*invalid = 0x7f;
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return kind;
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}
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static const struct nvkm_mmu_func
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nv50_mmu = {
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.dma_bits = 40,
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.mmu = {{ -1, -1, NVIF_CLASS_MMU_NV50}},
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.mem = {{ -1, 0, NVIF_CLASS_MEM_NV50}, nv50_mem_new, nv50_mem_map },
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.vmm = {{ -1, -1, NVIF_CLASS_VMM_NV50}, nv50_vmm_new, false, 0x1400 },
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.kind = nv50_mmu_kind,
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};
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int
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nv50_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
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{
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return nvkm_mmu_new_(&nv50_mmu, device, index, pmmu);
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}
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