bcc0e65f47
- Fix a silly typo in virt_addr_valid which led to completely bogus
behavior (that happened to stop tripping up hardened usercopy despite
being broken).
- Fix UART parity setup on AR933x systems.
- A build fix for non-Linux build machines.
- Have the 'all' make target build DTBs, primarily to fit in with the
behavior of scripts/package/builddeb.
- Handle an execution hazard in TLB exceptions that use KScratch
registers, which could inadvertently clobber the $1 register on some
generally higher-end out-of-order CPUs.
- A MAINTAINERS update to fix the path to the NAND driver for Ingenic
systems.
-----BEGIN PGP SIGNATURE-----
iIsEABYIADMWIQRgLjeFAZEXQzy86/s+p5+stXUA3QUCXSDJfhUccGF1bC5idXJ0
b25AbWlwcy5jb20ACgkQPqefrLV1AN35ygEA30KckazfjbtmW0EqD+C19sgtbSS3
eCAiweHHwLJoyUUBAJ/HzlZ8ap2X9ilZuFdzKEf1igj5WsLIyrkl6kkauUEA
=DRYO
-----END PGP SIGNATURE-----
Merge tag 'mips_fixes_5.2_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS fixes from Paul Burton:
"A few more MIPS fixes:
- Fix a silly typo in virt_addr_valid which led to completely bogus
behavior (that happened to stop tripping up hardened usercopy
despite being broken).
- Fix UART parity setup on AR933x systems.
- A build fix for non-Linux build machines.
- Have the 'all' make target build DTBs, primarily to fit in with the
behavior of scripts/package/builddeb.
- Handle an execution hazard in TLB exceptions that use KScratch
registers, which could inadvertently clobber the $1 register on
some generally higher-end out-of-order CPUs.
- A MAINTAINERS update to fix the path to the NAND driver for Ingenic
systems"
* tag 'mips_fixes_5.2_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
MAINTAINERS: Correct path to moved files
MIPS: Add missing EHB in mtc0 -> mfc0 sequence.
MIPS: have "plain" make calls build dtbs for selected platforms
MIPS: fix build on non-linux hosts
MIPS: ath79: fix ar933x uart parity mode
MIPS: Fix bounds check virt_addr_valid
64 lines
2 KiB
C
64 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Atheros AR933X UART defines
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*
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* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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*/
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#ifndef __AR933X_UART_H
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#define __AR933X_UART_H
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#define AR933X_UART_REGS_SIZE 20
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#define AR933X_UART_FIFO_SIZE 16
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#define AR933X_UART_DATA_REG 0x00
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#define AR933X_UART_CS_REG 0x04
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#define AR933X_UART_CLOCK_REG 0x08
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#define AR933X_UART_INT_REG 0x0c
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#define AR933X_UART_INT_EN_REG 0x10
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#define AR933X_UART_DATA_TX_RX_MASK 0xff
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#define AR933X_UART_DATA_RX_CSR BIT(8)
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#define AR933X_UART_DATA_TX_CSR BIT(9)
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#define AR933X_UART_CS_PARITY_S 0
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#define AR933X_UART_CS_PARITY_M 0x3
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#define AR933X_UART_CS_PARITY_NONE 0
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#define AR933X_UART_CS_PARITY_ODD 2
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#define AR933X_UART_CS_PARITY_EVEN 3
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#define AR933X_UART_CS_IF_MODE_S 2
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#define AR933X_UART_CS_IF_MODE_M 0x3
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#define AR933X_UART_CS_IF_MODE_NONE 0
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#define AR933X_UART_CS_IF_MODE_DTE 1
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#define AR933X_UART_CS_IF_MODE_DCE 2
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#define AR933X_UART_CS_FLOW_CTRL_S 4
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#define AR933X_UART_CS_FLOW_CTRL_M 0x3
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#define AR933X_UART_CS_DMA_EN BIT(6)
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#define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
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#define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
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#define AR933X_UART_CS_TX_READY BIT(9)
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#define AR933X_UART_CS_RX_BREAK BIT(10)
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#define AR933X_UART_CS_TX_BREAK BIT(11)
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#define AR933X_UART_CS_HOST_INT BIT(12)
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#define AR933X_UART_CS_HOST_INT_EN BIT(13)
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#define AR933X_UART_CS_TX_BUSY BIT(14)
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#define AR933X_UART_CS_RX_BUSY BIT(15)
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#define AR933X_UART_CLOCK_STEP_M 0xffff
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#define AR933X_UART_CLOCK_SCALE_M 0xfff
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#define AR933X_UART_CLOCK_SCALE_S 16
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#define AR933X_UART_CLOCK_STEP_M 0xffff
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#define AR933X_UART_INT_RX_VALID BIT(0)
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#define AR933X_UART_INT_TX_READY BIT(1)
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#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2)
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#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3)
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#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4)
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#define AR933X_UART_INT_RX_PARITY_ERR BIT(5)
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#define AR933X_UART_INT_RX_BREAK_ON BIT(6)
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#define AR933X_UART_INT_RX_BREAK_OFF BIT(7)
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#define AR933X_UART_INT_RX_FULL BIT(8)
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#define AR933X_UART_INT_TX_EMPTY BIT(9)
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#define AR933X_UART_INT_ALLINTS 0x3ff
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#endif /* __AR933X_UART_H */
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