Wayne Lin d1fa156809 drm/amd/display: Support vertical interrupt 0 for all dcn ASIC ... [Why] When CONFIG_DRM_AMD_SECURE_DISPLAY is enabled, it will try to register vertical interrupt 0 for specific task. Currently, only dcn10 have defined relevant info for vertical interrupt 0. If we enable CONFIG_DRM_AMD_SECURE_DISPLAY for other dcn ASIC, will get DC_IRQ_SOURCE_INVALID while calling dc_interrupt_to_irq_source() and cause pointer errors. [How] Add support of vertical interrupt 0 for all dcn ASIC. v2: squash in build fix (Alex) Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-03-23 23:36:31 -04:00
..
irq_service_dcn20.c	drm/amd/display: Support vertical interrupt 0 for all dcn ASIC	2021-03-23 23:36:31 -04:00
irq_service_dcn20.h	drm/amd/display: Add DCN2 IRQ handling	2019-06-21 18:59:34 -05:00