761d86d37f
When connected to a host via xGMI, system fatal errors may trigger warm reset, driver has no change to query edc status before reset. Therefore in this case, driver should harvest previous error loging registers during boot, instead of only resetting them. v2: 1. IP's ras_manager object is created when its ras feature is enabled, so change to query edc status after amdgpu_ras_late_init called 2. change to enable watchdog timer after finishing gfx edc init Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reivewed-by: Hawking Zhang <hawking.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
40 lines
1.9 KiB
C
40 lines
1.9 KiB
C
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __GFX_V9_4_2_H__
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#define __GFX_V9_4_2_H__
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void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev,
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uint32_t first_vmid, uint32_t last_vmid);
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void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev,
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uint32_t die_id);
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void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev);
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void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev);
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int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void *inject_if);
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void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev);
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int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status);
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void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev);
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void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev);
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#endif /* __GFX_V9_4_2_H__ */
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