b508079bf2
The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren <tony@atomide.com>
118 lines
2.5 KiB
Text
118 lines
2.5 KiB
Text
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Device Tree Source for OMAP36xx clock data
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*/
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&cm_clocks {
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dpll4_ck: dpll4_ck@d00 {
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#clock-cells = <0>;
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compatible = "ti,omap3-dpll-per-j-type-clock";
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clocks = <&sys_ck>, <&sys_ck>;
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reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
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};
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dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
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#clock-cells = <0>;
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compatible = "ti,hsdiv-gate-clock";
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clocks = <&dpll4_m5x2_mul_ck>;
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ti,bit-shift = <0x1e>;
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reg = <0x0d00>;
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ti,set-rate-parent;
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ti,set-bit-to-disable;
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};
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dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
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#clock-cells = <0>;
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compatible = "ti,hsdiv-gate-clock";
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clocks = <&dpll4_m2x2_mul_ck>;
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ti,bit-shift = <0x1b>;
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reg = <0x0d00>;
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ti,set-bit-to-disable;
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};
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dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
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#clock-cells = <0>;
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compatible = "ti,hsdiv-gate-clock";
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clocks = <&dpll3_m3x2_mul_ck>;
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ti,bit-shift = <0xc>;
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reg = <0x0d00>;
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ti,set-bit-to-disable;
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};
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dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
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#clock-cells = <0>;
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compatible = "ti,hsdiv-gate-clock";
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clocks = <&dpll4_m3x2_mul_ck>;
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ti,bit-shift = <0x1c>;
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reg = <0x0d00>;
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ti,set-bit-to-disable;
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};
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dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
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#clock-cells = <0>;
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compatible = "ti,hsdiv-gate-clock";
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clocks = <&dpll4_m6x2_mul_ck>;
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ti,bit-shift = <0x1f>;
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reg = <0x0d00>;
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ti,set-bit-to-disable;
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};
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clock@1000 {
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compatible = "ti,clksel";
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reg = <0x1000>;
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#clock-cells = <2>;
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#address-cells = <0>;
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uart4_fck: clock-uart4-fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clock-output-names = "uart4_fck";
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clocks = <&per_48m_fck>;
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ti,bit-shift = <18>;
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};
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};
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};
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&dpll4_m2x2_mul_ck {
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clock-mult = <1>;
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};
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&dpll4_m3x2_mul_ck {
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clock-mult = <1>;
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};
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&dpll4_m4x2_mul_ck {
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ti,clock-mult = <1>;
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};
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&dpll4_m5x2_mul_ck {
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ti,clock-mult = <1>;
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};
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&dpll4_m6x2_mul_ck {
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clock-mult = <1>;
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};
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&cm_clockdomains {
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dpll4_clkdm: dpll4_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&dpll4_ck>;
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};
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per_clkdm: per_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
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<&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
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<&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
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<&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
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<&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
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<&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
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<&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
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<&mcbsp4_ick>, <&uart4_fck>;
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};
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};
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&dpll4_m4_ck {
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ti,max-div = <31>;
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};
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