cfd7ea394c
LSE clock is provided by SCMI. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
84 lines
1.6 KiB
Text
84 lines
1.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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/dts-v1/;
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#include "stm32mp157c-ed1.dts"
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#include "stm32mp15-scmi.dtsi"
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/ {
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model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter";
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compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157";
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reserved-memory {
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optee@fe000000 {
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reg = <0xfe000000 0x2000000>;
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no-map;
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};
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};
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};
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&cpu0 {
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clocks = <&scmi_clk CK_SCMI_MPU>;
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};
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&cpu1 {
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clocks = <&scmi_clk CK_SCMI_MPU>;
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};
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&cryp1 {
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clocks = <&scmi_clk CK_SCMI_CRYP1>;
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resets = <&scmi_reset RST_SCMI_CRYP1>;
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};
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&dsi {
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clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
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};
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&gpioz {
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clocks = <&scmi_clk CK_SCMI_GPIOZ>;
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};
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&hash1 {
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clocks = <&scmi_clk CK_SCMI_HASH1>;
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resets = <&scmi_reset RST_SCMI_HASH1>;
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};
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&i2c4 {
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clocks = <&scmi_clk CK_SCMI_I2C4>;
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resets = <&scmi_reset RST_SCMI_I2C4>;
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};
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&iwdg2 {
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clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
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};
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&mdma1 {
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resets = <&scmi_reset RST_SCMI_MDMA>;
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};
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&mlahb {
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resets = <&scmi_reset RST_SCMI_MCU>;
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};
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&rcc {
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compatible = "st,stm32mp1-rcc-secure", "syscon";
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clock-names = "hse", "hsi", "csi", "lse", "lsi";
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clocks = <&scmi_clk CK_SCMI_HSE>,
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<&scmi_clk CK_SCMI_HSI>,
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<&scmi_clk CK_SCMI_CSI>,
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<&scmi_clk CK_SCMI_LSE>,
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<&scmi_clk CK_SCMI_LSI>;
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};
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&rng1 {
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clocks = <&scmi_clk CK_SCMI_RNG1>;
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resets = <&scmi_reset RST_SCMI_RNG1>;
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};
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&rtc {
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clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
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};
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