3976d758e0
As usual, the bulk of the changes for the SoC tree are devicetree file
updates, and most of these changes are for 64-bit embedded machines.
As before, there are a ton of style cleanups, and additional hardware
support for existing machines.
Looking only at the new SoC, the notable additions are:
- A whole family of Broadcom broadband SoCs, both 32-bit and 64-bit:
BCM63178, BCM63158, BCM4912, BCM6858, BCM6878, BCM6846, BCM63146,
BCM6856, BCM6855, BCM6756, BCM63148, and BCM6813.
Each SoC comes with a corresponding reference board.
- The new NXP i.MX93 SoC, the follow-up to the popular i.MX6 and
i.MX8 embedded SoCs, now using Cortex-A55 cores and the
Ethos-U65 NPU.
- Qualcomm Snapdragon 8cx Gen3 (SC8280XP), the current high end
of Arm based Laptop SoCs, and its automotive cousin, the
SA8540P. The SC8280XP is used in the Lenovo Thinkpad X13s
laptop that also gets added here in addition to the reference
boards.
- Allwinner H616, a newer version of the H6 SoC, targeted at
Set-top-box applications. It comes with dts files for the
Orange Pi zero2 single-board computer and the X96 Mate
set-top-box
- Marvell Prestera 98DX2530 (AlleyCat5), a network switch chip
in the Armada SoC family based on the Cortex-A55 core.
New machines based on previously supported SoCs include:
- Several new machines on NXP i.MX platforms: multiple Toradex
Colibri boards using the "Iris" and "Ixora" carriers,
DH electronics i.MX8M Plus DHCOM and PDK2, TQ-Systems
TQMa8MPQL, and phytech phyBOARD-Polis-i.MX8MM.
- Google Chameleon v3 FPGA board based on Intel Arria10 and
Stratix 10 Software Virtual platform, both in the SoCFPGA
platform.
- Two new wireless devices based on Broadcom SoCs:
The Asus GT-AX6000 Router and the Cisco Meraki MR26 access point
- Improved Chromebook support for both the Mediatek and Qualcomm
SoC families brought added machines: Acer Chromebook 514 (MT8192),
Acer Chromebook Spin 513 (MT8195) and a couple of SC7180 based
machines including the Lenovo IdeaPad Chromebook Duet 3.
- Xiaomi Mi Mix2s, LG G7 and LG V35 are mobile phones based on
Qualcomm SDM845, while Mi 5s Plus is based on MSM8996.
- Finally, there are a few development board on other chips:
PCB8309 (Microchip lan966x), Radxa Rock Pi S (Rockchips RK3308)
DH DRC Compact (ST STM32MP1) and Inforce IFC6560 (Qualcomm
SDM660)
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Merge tag 'arm-dt-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM DT updates from Arnd Bergmann:
"As usual, the bulk of the changes for the SoC tree are devicetree file
updates, and most of these changes are for 64-bit embedded machines.
As before, there are a ton of style cleanups, and additional hardware
support for existing machines.
Looking only at the new SoC, the notable additions are:
- A whole family of Broadcom broadband SoCs, both 32-bit and 64-bit:
BCM63178, BCM63158, BCM4912, BCM6858, BCM6878, BCM6846, BCM63146,
BCM6856, BCM6855, BCM6756, BCM63148, and BCM6813. Each SoC comes
with a corresponding reference board.
- The new NXP i.MX93 SoC, the follow-up to the popular i.MX6 and
i.MX8 embedded SoCs, now using Cortex-A55 cores and the Ethos-U65
NPU.
- Qualcomm Snapdragon 8cx Gen3 (SC8280XP), the current high end of
Arm based Laptop SoCs, and its automotive cousin, the SA8540P. The
SC8280XP is used in the Lenovo Thinkpad X13s laptop that also gets
added here in addition to the reference boards.
- Allwinner H616, a newer version of the H6 SoC, targeted at
Set-top-box applications. It comes with dts files for the Orange Pi
zero2 single-board computer and the X96 Mate set-top-box
- Marvell Prestera 98DX2530 (AlleyCat5), a network switch chip in the
Armada SoC family based on the Cortex-A55 core.
New machines based on previously supported SoCs include:
- Several new machines on NXP i.MX platforms: multiple Toradex
Colibri boards using the "Iris" and "Ixora" carriers, DH
electronics i.MX8M Plus DHCOM and PDK2, TQ-Systems TQMa8MPQL, and
phytech phyBOARD-Polis-i.MX8MM.
- Google Chameleon v3 FPGA board based on Intel Arria10 and Stratix
10 Software Virtual platform, both in the SoCFPGA platform.
- Two new wireless devices based on Broadcom SoCs: The Asus GT-AX6000
Router and the Cisco Meraki MR26 access point
- Improved Chromebook support for both the Mediatek and Qualcomm SoC
families brought added machines: Acer Chromebook 514 (MT8192), Acer
Chromebook Spin 513 (MT8195) and a couple of SC7180 based machines
including the Lenovo IdeaPad Chromebook Duet 3.
- Xiaomi Mi Mix2s, LG G7 and LG V35 are mobile phones based on
Qualcomm SDM845, while Mi 5s Plus is based on MSM8996.
- Finally, there are a few development board on other chips: PCB8309
(Microchip lan966x), Radxa Rock Pi S (Rockchips RK3308) DH DRC
Compact (ST STM32MP1) and Inforce IFC6560 (Qualcomm SDM660)"
* tag 'arm-dt-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (829 commits)
dt-bindings: soc: bcm: use absolute path to other schema
dt-bindings: soc: bcm: drop quotes when not needed
dt-bindings: soc: microchip: use absolute path to other schema
dt-bindings: soc: microchip: drop quotes when not needed
ARM: dts: lan966x: keep lan966 entries alphabetically sorted
ARM: dts: lan966x: add support for pcb8309
dt-bindings: arm: at91: add lan966 pcb8309 board
ARM: dts: lan966x: Enable network driver on pcb8291
ARM: dts: lan966x: Disable can0 on pcb8291
ARM: dts: lan966x: Add gpio-restart
dt-bindings: arm: aspeed: add Aspeed Evaluation boards
arm64: dts: qcom: Add support for Xiaomi Mi Mix2s
dt-bindings: arm: qcom: Add Xiaomi Mi Mix2s bindings
dt-bindings: arm: qcom: Document lg,judyln and lg,judyp devices
dt-bindings: arm: qcom: add missing SM6350 board compatibles
dt-bindings: arm: qcom: add missing SM6125 board compatibles
dt-bindings: arm: qcom: add missing SDM845 board compatibles
dt-bindings: arm: qcom: add missing SDM636 board compatibles
dt-bindings: arm: qcom: add missing SDM630 board compatibles
dt-bindings: arm: qcom: add missing QCS404 board compatibles
...
1249 lines
34 KiB
Text
1249 lines
34 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019 NXP
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*/
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#include <dt-bindings/clock/imx8mp-clock.h>
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#include <dt-bindings/power/imx8mp-power.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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#include "imx8mp-pinfunc.h"
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &fec;
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ethernet1 = &eqos;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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i2c4 = &i2c5;
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i2c5 = &i2c6;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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spi0 = &flexspi;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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A53_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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clock-latency = <61036>;
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clocks = <&clk IMX8MP_CLK_ARM>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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nvmem-cells = <&cpu_speed_grade>;
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nvmem-cell-names = "speed_grade";
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operating-points-v2 = <&a53_opp_table>;
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#cooling-cells = <2>;
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};
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A53_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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clock-latency = <61036>;
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clocks = <&clk IMX8MP_CLK_ARM>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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#cooling-cells = <2>;
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};
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A53_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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clock-latency = <61036>;
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clocks = <&clk IMX8MP_CLK_ARM>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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#cooling-cells = <2>;
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};
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A53_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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clock-latency = <61036>;
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clocks = <&clk IMX8MP_CLK_ARM>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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#cooling-cells = <2>;
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};
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A53_L2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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};
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};
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a53_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <850000>;
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opp-supported-hw = <0x8a0>, <0x7>;
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clock-latency-ns = <150000>;
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opp-suspend;
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};
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opp-1600000000 {
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opp-hz = /bits/ 64 <1600000000>;
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opp-microvolt = <950000>;
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opp-supported-hw = <0xa0>, <0x7>;
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clock-latency-ns = <150000>;
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opp-suspend;
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};
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1000000>;
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opp-supported-hw = <0x20>, <0x3>;
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clock-latency-ns = <150000>;
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opp-suspend;
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};
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};
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osc_32k: clock-osc-32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "osc_32k";
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};
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osc_24m: clock-osc-24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "osc_24m";
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};
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clk_ext1: clock-ext1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext1";
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};
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clk_ext2: clock-ext2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext2";
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};
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clk_ext3: clock-ext3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext3";
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};
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clk_ext4: clock-ext4 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext4";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dsp_reserved: dsp@92400000 {
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reg = <0 0x92400000 0 0x2000000>;
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no-map;
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};
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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thermal-zones {
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cpu-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tmu 0>;
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trips {
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cpu_alert0: trip0 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit0: trip1 {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device =
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<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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soc-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tmu 1>;
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trips {
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soc_alert0: trip0 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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soc_crit0: trip1 {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&soc_alert0>;
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cooling-device =
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<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <8000000>;
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arm,no-tick-in-suspend;
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};
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soc: soc@0 {
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compatible = "fsl,imx8mp-soc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x3e000000>;
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nvmem-cells = <&imx8mp_uid>;
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nvmem-cell-names = "soc_unique_id";
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aips1: bus@30000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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reg = <0x30000000 0x400000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio1: gpio@30200000 {
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compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
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reg = <0x30200000 0x10000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&iomuxc 0 5 30>;
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};
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gpio2: gpio@30210000 {
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compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
|
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reg = <0x30210000 0x10000>;
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|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&iomuxc 0 35 21>;
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};
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gpio3: gpio@30220000 {
|
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compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
|
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reg = <0x30220000 0x10000>;
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|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
|
|
};
|
|
|
|
gpio4: gpio@30230000 {
|
|
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30230000 0x10000>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 82 32>;
|
|
};
|
|
|
|
gpio5: gpio@30240000 {
|
|
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30240000 0x10000>;
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 114 30>;
|
|
};
|
|
|
|
tmu: tmu@30260000 {
|
|
compatible = "fsl,imx8mp-tmu";
|
|
reg = <0x30260000 0x10000>;
|
|
clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
wdog1: watchdog@30280000 {
|
|
compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
|
|
reg = <0x30280000 0x10000>;
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog2: watchdog@30290000 {
|
|
compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
|
|
reg = <0x30290000 0x10000>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog3: watchdog@302a0000 {
|
|
compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
|
|
reg = <0x302a0000 0x10000>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iomuxc: pinctrl@30330000 {
|
|
compatible = "fsl,imx8mp-iomuxc";
|
|
reg = <0x30330000 0x10000>;
|
|
};
|
|
|
|
gpr: iomuxc-gpr@30340000 {
|
|
compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
|
|
reg = <0x30340000 0x10000>;
|
|
};
|
|
|
|
ocotp: efuse@30350000 {
|
|
compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
|
|
reg = <0x30350000 0x10000>;
|
|
clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
|
|
/* For nvmem subnodes */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
imx8mp_uid: unique-id@420 {
|
|
reg = <0x8 0x8>;
|
|
};
|
|
|
|
cpu_speed_grade: speed-grade@10 {
|
|
reg = <0x10 4>;
|
|
};
|
|
|
|
eth_mac1: mac-address@90 {
|
|
reg = <0x90 6>;
|
|
};
|
|
|
|
eth_mac2: mac-address@96 {
|
|
reg = <0x96 6>;
|
|
};
|
|
};
|
|
|
|
anatop: anatop@30360000 {
|
|
compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
|
|
"syscon";
|
|
reg = <0x30360000 0x10000>;
|
|
};
|
|
|
|
snvs: snvs@30370000 {
|
|
compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
|
|
reg = <0x30370000 0x10000>;
|
|
|
|
snvs_rtc: snvs-rtc-lp {
|
|
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
|
regmap =<&snvs>;
|
|
offset = <0x34>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
|
|
clock-names = "snvs-rtc";
|
|
};
|
|
|
|
snvs_pwrkey: snvs-powerkey {
|
|
compatible = "fsl,sec-v4.0-pwrkey";
|
|
regmap = <&snvs>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
|
|
clock-names = "snvs-pwrkey";
|
|
linux,keycode = <KEY_POWER>;
|
|
wakeup-source;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
clk: clock-controller@30380000 {
|
|
compatible = "fsl,imx8mp-ccm";
|
|
reg = <0x30380000 0x10000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
|
|
<&clk_ext3>, <&clk_ext4>;
|
|
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
|
"clk_ext3", "clk_ext4";
|
|
assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
|
|
<&clk IMX8MP_CLK_A53_CORE>,
|
|
<&clk IMX8MP_CLK_NOC>,
|
|
<&clk IMX8MP_CLK_NOC_IO>,
|
|
<&clk IMX8MP_CLK_GIC>,
|
|
<&clk IMX8MP_CLK_AUDIO_AHB>,
|
|
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
|
|
<&clk IMX8MP_AUDIO_PLL1>,
|
|
<&clk IMX8MP_AUDIO_PLL2>;
|
|
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
|
|
<&clk IMX8MP_ARM_PLL_OUT>,
|
|
<&clk IMX8MP_SYS_PLL2_1000M>,
|
|
<&clk IMX8MP_SYS_PLL1_800M>,
|
|
<&clk IMX8MP_SYS_PLL2_500M>,
|
|
<&clk IMX8MP_SYS_PLL1_800M>,
|
|
<&clk IMX8MP_SYS_PLL1_800M>;
|
|
assigned-clock-rates = <0>, <0>,
|
|
<1000000000>,
|
|
<800000000>,
|
|
<500000000>,
|
|
<400000000>,
|
|
<800000000>,
|
|
<393216000>,
|
|
<361267200>;
|
|
};
|
|
|
|
src: reset-controller@30390000 {
|
|
compatible = "fsl,imx8mp-src", "syscon";
|
|
reg = <0x30390000 0x10000>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpc: gpc@303a0000 {
|
|
compatible = "fsl,imx8mp-gpc";
|
|
reg = <0x303a0000 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
|
|
pgc {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pgc_mipi_phy1: power-domain@0 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
|
|
};
|
|
|
|
pgc_pcie_phy: power-domain@1 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
|
|
};
|
|
|
|
pgc_usb1_phy: power-domain@2 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
|
|
};
|
|
|
|
pgc_usb2_phy: power-domain@3 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
|
|
};
|
|
|
|
pgc_gpu2d: power-domain@6 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
|
|
clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
|
|
power-domains = <&pgc_gpumix>;
|
|
};
|
|
|
|
pgc_gpumix: power-domain@7 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
|
|
clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
|
|
<&clk IMX8MP_CLK_GPU_AHB>;
|
|
assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
|
|
<&clk IMX8MP_CLK_GPU_AHB>;
|
|
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
|
|
<&clk IMX8MP_SYS_PLL1_800M>;
|
|
assigned-clock-rates = <800000000>, <400000000>;
|
|
};
|
|
|
|
pgc_gpu3d: power-domain@9 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
|
|
clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
|
|
<&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
|
|
power-domains = <&pgc_gpumix>;
|
|
};
|
|
|
|
pgc_mediamix: power-domain@10 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
|
|
clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
|
|
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
|
|
};
|
|
|
|
pgc_mipi_phy2: power-domain@16 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
|
|
};
|
|
|
|
pgc_hsiomix: power-domains@17 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
|
|
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
|
|
<&clk IMX8MP_CLK_HSIO_ROOT>;
|
|
assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
|
|
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
|
|
assigned-clock-rates = <500000000>;
|
|
};
|
|
|
|
pgc_ispdwp: power-domain@18 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
|
|
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
aips2: bus@30400000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
reg = <0x30400000 0x400000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
pwm1: pwm@30660000 {
|
|
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30660000 0x10000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
|
|
<&clk IMX8MP_CLK_PWM1_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@30670000 {
|
|
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30670000 0x10000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
|
|
<&clk IMX8MP_CLK_PWM2_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@30680000 {
|
|
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30680000 0x10000>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
|
|
<&clk IMX8MP_CLK_PWM3_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm4: pwm@30690000 {
|
|
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30690000 0x10000>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
|
|
<&clk IMX8MP_CLK_PWM4_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
system_counter: timer@306a0000 {
|
|
compatible = "nxp,sysctr-timer";
|
|
reg = <0x306a0000 0x20000>;
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&osc_24m>;
|
|
clock-names = "per";
|
|
};
|
|
};
|
|
|
|
aips3: bus@30800000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
reg = <0x30800000 0x400000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
ecspi1: spi@30820000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x30820000 0x10000>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
|
|
<&clk IMX8MP_CLK_ECSPI1_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi2: spi@30830000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x30830000 0x10000>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
|
|
<&clk IMX8MP_CLK_ECSPI2_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi3: spi@30840000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x30840000 0x10000>;
|
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
|
|
<&clk IMX8MP_CLK_ECSPI3_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@30860000 {
|
|
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
|
|
reg = <0x30860000 0x10000>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
|
|
<&clk IMX8MP_CLK_UART1_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@30880000 {
|
|
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
|
|
reg = <0x30880000 0x10000>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
|
|
<&clk IMX8MP_CLK_UART3_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@30890000 {
|
|
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
|
|
reg = <0x30890000 0x10000>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
|
|
<&clk IMX8MP_CLK_UART2_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
flexcan1: can@308c0000 {
|
|
compatible = "fsl,imx8mp-flexcan";
|
|
reg = <0x308c0000 0x10000>;
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
|
|
<&clk IMX8MP_CLK_CAN1_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
|
|
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
|
|
assigned-clock-rates = <40000000>;
|
|
fsl,clk-source = /bits/ 8 <0>;
|
|
fsl,stop-mode = <&gpr 0x10 4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexcan2: can@308d0000 {
|
|
compatible = "fsl,imx8mp-flexcan";
|
|
reg = <0x308d0000 0x10000>;
|
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
|
|
<&clk IMX8MP_CLK_CAN2_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
|
|
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
|
|
assigned-clock-rates = <40000000>;
|
|
fsl,clk-source = /bits/ 8 <0>;
|
|
fsl,stop-mode = <&gpr 0x10 5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
crypto: crypto@30900000 {
|
|
compatible = "fsl,sec-v4.0";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x30900000 0x40000>;
|
|
ranges = <0 0x30900000 0x40000>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_AHB>,
|
|
<&clk IMX8MP_CLK_IPG_ROOT>;
|
|
clock-names = "aclk", "ipg";
|
|
|
|
sec_jr0: jr@1000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x1000 0x1000>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sec_jr1: jr@2000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x2000 0x1000>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr2: jr@3000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x3000 0x1000>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
i2c1: i2c@30a20000 {
|
|
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x30a20000 0x10000>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@30a30000 {
|
|
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x30a30000 0x10000>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@30a40000 {
|
|
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x30a40000 0x10000>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@30a50000 {
|
|
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x30a50000 0x10000>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@30a60000 {
|
|
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
|
|
reg = <0x30a60000 0x10000>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
|
|
<&clk IMX8MP_CLK_UART4_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
mu: mailbox@30aa0000 {
|
|
compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
|
|
reg = <0x30aa0000 0x10000>;
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_MU_ROOT>;
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
mu2: mailbox@30e60000 {
|
|
compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
|
|
reg = <0x30e60000 0x10000>;
|
|
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@30ad0000 {
|
|
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x30ad0000 0x10000>;
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c6: i2c@30ae0000 {
|
|
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x30ae0000 0x10000>;
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc1: mmc@30b40000 {
|
|
compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
|
|
reg = <0x30b40000 0x10000>;
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_DUMMY>,
|
|
<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
|
|
<&clk IMX8MP_CLK_USDHC1_ROOT>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step = <2>;
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc2: mmc@30b50000 {
|
|
compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
|
|
reg = <0x30b50000 0x10000>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_DUMMY>,
|
|
<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
|
|
<&clk IMX8MP_CLK_USDHC2_ROOT>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step = <2>;
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc3: mmc@30b60000 {
|
|
compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
|
|
reg = <0x30b60000 0x10000>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_DUMMY>,
|
|
<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
|
|
<&clk IMX8MP_CLK_USDHC3_ROOT>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step = <2>;
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexspi: spi@30bb0000 {
|
|
compatible = "nxp,imx8mp-fspi";
|
|
reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
|
|
reg-names = "fspi_base", "fspi_mmap";
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
|
|
<&clk IMX8MP_CLK_QSPI_ROOT>;
|
|
clock-names = "fspi_en", "fspi";
|
|
assigned-clock-rates = <80000000>;
|
|
assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdma1: dma-controller@30bd0000 {
|
|
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
|
|
reg = <0x30bd0000 0x10000>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
|
|
<&clk IMX8MP_CLK_AHB>;
|
|
clock-names = "ipg", "ahb";
|
|
#dma-cells = <3>;
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
|
};
|
|
|
|
fec: ethernet@30be0000 {
|
|
compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
|
|
reg = <0x30be0000 0x10000>;
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
|
|
<&clk IMX8MP_CLK_SIM_ENET_ROOT>,
|
|
<&clk IMX8MP_CLK_ENET_TIMER>,
|
|
<&clk IMX8MP_CLK_ENET_REF>,
|
|
<&clk IMX8MP_CLK_ENET_PHY_REF>;
|
|
clock-names = "ipg", "ahb", "ptp",
|
|
"enet_clk_ref", "enet_out";
|
|
assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
|
|
<&clk IMX8MP_CLK_ENET_TIMER>,
|
|
<&clk IMX8MP_CLK_ENET_REF>,
|
|
<&clk IMX8MP_CLK_ENET_PHY_REF>;
|
|
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
|
|
<&clk IMX8MP_SYS_PLL2_100M>,
|
|
<&clk IMX8MP_SYS_PLL2_125M>,
|
|
<&clk IMX8MP_SYS_PLL2_50M>;
|
|
assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
|
|
fsl,num-tx-queues = <3>;
|
|
fsl,num-rx-queues = <3>;
|
|
nvmem-cells = <ð_mac1>;
|
|
nvmem-cell-names = "mac-address";
|
|
fsl,stop-mode = <&gpr 0x10 3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
eqos: ethernet@30bf0000 {
|
|
compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
|
|
reg = <0x30bf0000 0x10000>;
|
|
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq", "eth_wake_irq";
|
|
clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
|
|
<&clk IMX8MP_CLK_QOS_ENET_ROOT>,
|
|
<&clk IMX8MP_CLK_ENET_QOS_TIMER>,
|
|
<&clk IMX8MP_CLK_ENET_QOS>;
|
|
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
|
|
assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
|
|
<&clk IMX8MP_CLK_ENET_QOS_TIMER>,
|
|
<&clk IMX8MP_CLK_ENET_QOS>;
|
|
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
|
|
<&clk IMX8MP_SYS_PLL2_100M>,
|
|
<&clk IMX8MP_SYS_PLL2_125M>;
|
|
assigned-clock-rates = <0>, <100000000>, <125000000>;
|
|
nvmem-cells = <ð_mac2>;
|
|
nvmem-cell-names = "mac-address";
|
|
intf_mode = <&gpr 0x4>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
noc: interconnect@32700000 {
|
|
compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
|
|
reg = <0x32700000 0x100000>;
|
|
clocks = <&clk IMX8MP_CLK_NOC>;
|
|
#interconnect-cells = <1>;
|
|
operating-points-v2 = <&noc_opp_table>;
|
|
|
|
noc_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-200M {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
};
|
|
|
|
opp-1000M {
|
|
opp-hz = /bits/ 64 <1000000000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
aips4: bus@32c00000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
reg = <0x32c00000 0x400000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
media_blk_ctrl: blk-ctrl@32ec0000 {
|
|
compatible = "fsl,imx8mp-media-blk-ctrl",
|
|
"syscon";
|
|
reg = <0x32ec0000 0x10000>;
|
|
power-domains = <&pgc_mediamix>,
|
|
<&pgc_mipi_phy1>,
|
|
<&pgc_mipi_phy1>,
|
|
<&pgc_mediamix>,
|
|
<&pgc_mediamix>,
|
|
<&pgc_mipi_phy2>,
|
|
<&pgc_mediamix>,
|
|
<&pgc_ispdwp>,
|
|
<&pgc_ispdwp>,
|
|
<&pgc_mipi_phy2>;
|
|
power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
|
|
"lcdif1", "isi", "mipi-csi2",
|
|
"lcdif2", "isp", "dwe",
|
|
"mipi-dsi2";
|
|
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
|
|
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
|
|
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
|
|
<&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
|
|
<&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
|
|
<&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
|
|
<&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
|
|
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
|
|
clock-names = "apb", "axi", "cam1", "cam2",
|
|
"disp1", "disp2", "isp", "phy";
|
|
|
|
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
|
|
<&clk IMX8MP_CLK_MEDIA_APB>;
|
|
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
|
|
<&clk IMX8MP_SYS_PLL1_800M>;
|
|
assigned-clock-rates = <500000000>, <200000000>;
|
|
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
hsio_blk_ctrl: blk-ctrl@32f10000 {
|
|
compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
|
|
reg = <0x32f10000 0x24>;
|
|
clocks = <&clk IMX8MP_CLK_USB_ROOT>,
|
|
<&clk IMX8MP_CLK_PCIE_ROOT>;
|
|
clock-names = "usb", "pcie";
|
|
power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
|
|
<&pgc_usb1_phy>, <&pgc_usb2_phy>,
|
|
<&pgc_hsiomix>, <&pgc_pcie_phy>;
|
|
power-domain-names = "bus", "usb", "usb-phy1",
|
|
"usb-phy2", "pcie", "pcie-phy";
|
|
#power-domain-cells = <1>;
|
|
};
|
|
};
|
|
|
|
gpu3d: gpu@38000000 {
|
|
compatible = "vivante,gc";
|
|
reg = <0x38000000 0x8000>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
|
|
<&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
|
|
<&clk IMX8MP_CLK_GPU_ROOT>,
|
|
<&clk IMX8MP_CLK_GPU_AHB>;
|
|
clock-names = "core", "shader", "bus", "reg";
|
|
assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
|
|
<&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
|
|
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
|
|
<&clk IMX8MP_SYS_PLL1_800M>;
|
|
assigned-clock-rates = <800000000>, <800000000>;
|
|
power-domains = <&pgc_gpu3d>;
|
|
};
|
|
|
|
gpu2d: gpu@38008000 {
|
|
compatible = "vivante,gc";
|
|
reg = <0x38008000 0x8000>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
|
|
<&clk IMX8MP_CLK_GPU_ROOT>,
|
|
<&clk IMX8MP_CLK_GPU_AHB>;
|
|
clock-names = "core", "bus", "reg";
|
|
assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
|
|
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
|
|
assigned-clock-rates = <800000000>;
|
|
power-domains = <&pgc_gpu2d>;
|
|
};
|
|
|
|
gic: interrupt-controller@38800000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x38800000 0x10000>,
|
|
<0x38880000 0xc0000>;
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-parent = <&gic>;
|
|
};
|
|
|
|
edacmc: memory-controller@3d400000 {
|
|
compatible = "snps,ddrc-3.80a";
|
|
reg = <0x3d400000 0x400000>;
|
|
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
ddr-pmu@3d800000 {
|
|
compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
|
|
reg = <0x3d800000 0x400000>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
usb3_phy0: usb-phy@381f0040 {
|
|
compatible = "fsl,imx8mp-usb-phy";
|
|
reg = <0x381f0040 0x40>;
|
|
clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
|
|
clock-names = "phy";
|
|
assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
|
|
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
|
|
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3_0: usb@32f10100 {
|
|
compatible = "fsl,imx8mp-dwc3";
|
|
reg = <0x32f10100 0x8>,
|
|
<0x381f0000 0x20>;
|
|
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
|
|
<&clk IMX8MP_CLK_USB_ROOT>;
|
|
clock-names = "hsio", "suspend";
|
|
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
usb_dwc3_0: usb@38100000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x38100000 0x10000>;
|
|
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
|
|
<&clk IMX8MP_CLK_USB_CORE_REF>,
|
|
<&clk IMX8MP_CLK_USB_ROOT>;
|
|
clock-names = "bus_early", "ref", "suspend";
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&usb3_phy0>, <&usb3_phy0>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
snps,dis-u2-freeclk-exists-quirk;
|
|
};
|
|
|
|
};
|
|
|
|
usb3_phy1: usb-phy@382f0040 {
|
|
compatible = "fsl,imx8mp-usb-phy";
|
|
reg = <0x382f0040 0x40>;
|
|
clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
|
|
clock-names = "phy";
|
|
assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
|
|
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
|
|
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3_1: usb@32f10108 {
|
|
compatible = "fsl,imx8mp-dwc3";
|
|
reg = <0x32f10108 0x8>,
|
|
<0x382f0000 0x20>;
|
|
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
|
|
<&clk IMX8MP_CLK_USB_ROOT>;
|
|
clock-names = "hsio", "suspend";
|
|
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
usb_dwc3_1: usb@38200000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x38200000 0x10000>;
|
|
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
|
|
<&clk IMX8MP_CLK_USB_CORE_REF>,
|
|
<&clk IMX8MP_CLK_USB_ROOT>;
|
|
clock-names = "bus_early", "ref", "suspend";
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&usb3_phy1>, <&usb3_phy1>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
snps,dis-u2-freeclk-exists-quirk;
|
|
};
|
|
};
|
|
|
|
dsp: dsp@3b6e8000 {
|
|
compatible = "fsl,imx8mp-dsp";
|
|
reg = <0x3b6e8000 0x88000>;
|
|
mbox-names = "txdb0", "txdb1",
|
|
"rxdb0", "rxdb1";
|
|
mboxes = <&mu2 2 0>, <&mu2 2 1>,
|
|
<&mu2 3 0>, <&mu2 3 1>;
|
|
memory-region = <&dsp_reserved>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|