9290c379d1
In the same spirit as commit 63f501e07a ("powerpc/8xx: Simplify TLB
handling"), simplify flush_tlb_kernel_range() for 8xx.
8xx cannot be SMP, and has 'tlbie' and 'tlbia' instructions, so
an inline version of flush_tlb_kernel_range() for 8xx is worth it.
With this page, first leg of change_page_attr() is:
2c: 55 29 00 3c rlwinm r9,r9,0,0,30
30: 91 23 00 00 stw r9,0(r3)
34: 7c 00 22 64 tlbie r4,r0
38: 7c 00 04 ac hwsync
3c: 38 60 00 00 li r3,0
40: 4e 80 00 20 blr
Before the patch it was:
30: 55 29 00 3c rlwinm r9,r9,0,0,30
34: 91 2a 00 00 stw r9,0(r10)
38: 94 21 ff f0 stwu r1,-16(r1)
3c: 7c 08 02 a6 mflr r0
40: 38 83 10 00 addi r4,r3,4096
44: 90 01 00 14 stw r0,20(r1)
48: 48 00 00 01 bl 48 <change_page_attr+0x48>
48: R_PPC_REL24 flush_tlb_kernel_range
4c: 80 01 00 14 lwz r0,20(r1)
50: 38 60 00 00 li r3,0
54: 7c 08 03 a6 mtlr r0
58: 38 21 00 10 addi r1,r1,16
5c: 4e 80 00 20 blr
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/d2610043419ce3e0e53a85386baf2c3625af5cfb.1647877442.git.christophe.leroy@csgroup.eu
77 lines
2.4 KiB
C
77 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_NOHASH_TLBFLUSH_H
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#define _ASM_POWERPC_NOHASH_TLBFLUSH_H
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/*
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* TLB flushing:
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*
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - local_flush_tlb_mm(mm, full) flushes the specified mm context on
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* the local processor
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* - local_flush_tlb_page(vma, vmaddr) flushes one page on the local processor
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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*
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*/
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/*
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* TLB flushing for software loaded TLB chips
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*
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* TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range &
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* flush_tlb_kernel_range are best implemented as tlbia vs
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* specific tlbie's
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*/
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struct vm_area_struct;
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struct mm_struct;
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#define MMU_NO_CONTEXT ((unsigned int)-1)
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extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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#ifdef CONFIG_PPC_8xx
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static inline void local_flush_tlb_mm(struct mm_struct *mm)
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{
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unsigned int pid = READ_ONCE(mm->context.id);
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if (pid != MMU_NO_CONTEXT)
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asm volatile ("sync; tlbia; isync" : : : "memory");
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}
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static inline void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
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{
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asm volatile ("tlbie %0; sync" : : "r" (vmaddr) : "memory");
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}
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static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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start &= PAGE_MASK;
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if (end - start <= PAGE_SIZE)
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asm volatile ("tlbie %0; sync" : : "r" (start) : "memory");
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else
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asm volatile ("sync; tlbia; isync" : : : "memory");
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}
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#else
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extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
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extern void local_flush_tlb_mm(struct mm_struct *mm);
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extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
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extern void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
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int tsize, int ind);
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#endif
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#ifdef CONFIG_SMP
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extern void flush_tlb_mm(struct mm_struct *mm);
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extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
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extern void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
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int tsize, int ind);
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#else
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#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
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#define flush_tlb_page(vma,addr) local_flush_tlb_page(vma,addr)
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#define __flush_tlb_page(mm,addr,p,i) __local_flush_tlb_page(mm,addr,p,i)
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#endif
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#endif /* _ASM_POWERPC_NOHASH_TLBFLUSH_H */
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