Mark Kettenis a208acf0ea riscv: dts: starfive: correct number of external interrupts ... The PLIC integrated on the Vic_U7_Core integrated on the StarFive JH7100 SoC actually supports 133 external interrupts. 127 of these are exposed to the outside world; the remainder are used by other devices that are part of the core-complex such as the L2 cache controller. But all 133 interrupts are external interrupts as far as the PLIC is concerned. Fix the property so that the driver can manage these additional interrupts, which is important since the interrupts for the L2 cache controller are enabled by default. Fixes: ec85362fb1 ("RISC-V: Add initial StarFive JH7100 device tree") Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220707185529.19509-1-kettenis@openbsd.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2022-08-11 11:40:37 -07:00
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canaan	RISC-V: Canaan devicetree fixes	2022-08-10 14:43:14 -07:00
microchip	RISC-V Patches for the 5.20 Merge Window, Part 1	2022-08-06 15:04:48 -07:00
sifive	riscv: dts: sifive unmatched: Add PWM controlled LEDs	2022-08-11 11:34:57 -07:00
starfive	riscv: dts: starfive: correct number of external interrupts	2022-08-11 11:40:37 -07:00
Makefile	RISC-V: Add BeagleV Starlight Beta device tree	2021-12-16 17:24:23 +01:00