Sstc extension allows the guest to program the vstimecmp CSR directly instead of making an SBI call to the hypervisor to program the next event. The timer interrupt is also directly injected to the guest by the hardware in this case. To maintain backward compatibility, the hypervisors also update the vstimecmp in an SBI set_time call if the hardware supports it. Thus, the older kernels in guest also take advantage of the sstc extension. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> Acked-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/all/CAAhSdy2mb6wyqy0NAn9BcTWKMYEc0Z4zU3s3j7oNqBz6eDQ9sg@mail.gmail.com/ Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
355 lines
8.7 KiB
C
355 lines
8.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Atish Patra <atish.patra@wdc.com>
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*/
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/kvm_host.h>
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#include <linux/uaccess.h>
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#include <clocksource/timer-riscv.h>
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#include <asm/csr.h>
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#include <asm/delay.h>
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#include <asm/kvm_vcpu_timer.h>
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static u64 kvm_riscv_current_cycles(struct kvm_guest_timer *gt)
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{
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return get_cycles64() + gt->time_delta;
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}
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static u64 kvm_riscv_delta_cycles2ns(u64 cycles,
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struct kvm_guest_timer *gt,
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struct kvm_vcpu_timer *t)
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{
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unsigned long flags;
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u64 cycles_now, cycles_delta, delta_ns;
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local_irq_save(flags);
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cycles_now = kvm_riscv_current_cycles(gt);
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if (cycles_now < cycles)
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cycles_delta = cycles - cycles_now;
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else
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cycles_delta = 0;
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delta_ns = (cycles_delta * gt->nsec_mult) >> gt->nsec_shift;
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local_irq_restore(flags);
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return delta_ns;
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}
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static enum hrtimer_restart kvm_riscv_vcpu_hrtimer_expired(struct hrtimer *h)
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{
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u64 delta_ns;
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struct kvm_vcpu_timer *t = container_of(h, struct kvm_vcpu_timer, hrt);
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struct kvm_vcpu *vcpu = container_of(t, struct kvm_vcpu, arch.timer);
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struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
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if (kvm_riscv_current_cycles(gt) < t->next_cycles) {
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delta_ns = kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t);
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hrtimer_forward_now(&t->hrt, ktime_set(0, delta_ns));
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return HRTIMER_RESTART;
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}
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t->next_set = false;
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kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_VS_TIMER);
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return HRTIMER_NORESTART;
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}
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static int kvm_riscv_vcpu_timer_cancel(struct kvm_vcpu_timer *t)
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{
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if (!t->init_done || !t->next_set)
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return -EINVAL;
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hrtimer_cancel(&t->hrt);
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t->next_set = false;
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return 0;
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}
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static int kvm_riscv_vcpu_update_vstimecmp(struct kvm_vcpu *vcpu, u64 ncycles)
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{
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#if defined(CONFIG_32BIT)
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csr_write(CSR_VSTIMECMP, ncycles & 0xFFFFFFFF);
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csr_write(CSR_VSTIMECMPH, ncycles >> 32);
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#else
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csr_write(CSR_VSTIMECMP, ncycles);
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#endif
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return 0;
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}
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static int kvm_riscv_vcpu_update_hrtimer(struct kvm_vcpu *vcpu, u64 ncycles)
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{
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struct kvm_vcpu_timer *t = &vcpu->arch.timer;
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struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
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u64 delta_ns;
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if (!t->init_done)
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return -EINVAL;
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kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_TIMER);
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delta_ns = kvm_riscv_delta_cycles2ns(ncycles, gt, t);
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t->next_cycles = ncycles;
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hrtimer_start(&t->hrt, ktime_set(0, delta_ns), HRTIMER_MODE_REL);
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t->next_set = true;
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return 0;
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}
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int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles)
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{
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struct kvm_vcpu_timer *t = &vcpu->arch.timer;
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return t->timer_next_event(vcpu, ncycles);
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}
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static enum hrtimer_restart kvm_riscv_vcpu_vstimer_expired(struct hrtimer *h)
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{
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u64 delta_ns;
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struct kvm_vcpu_timer *t = container_of(h, struct kvm_vcpu_timer, hrt);
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struct kvm_vcpu *vcpu = container_of(t, struct kvm_vcpu, arch.timer);
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struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
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if (kvm_riscv_current_cycles(gt) < t->next_cycles) {
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delta_ns = kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t);
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hrtimer_forward_now(&t->hrt, ktime_set(0, delta_ns));
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return HRTIMER_RESTART;
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}
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t->next_set = false;
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kvm_vcpu_kick(vcpu);
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return HRTIMER_NORESTART;
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}
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bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu)
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{
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struct kvm_vcpu_timer *t = &vcpu->arch.timer;
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struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
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if (!kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t) ||
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kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER))
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return true;
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else
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return false;
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}
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static void kvm_riscv_vcpu_timer_blocking(struct kvm_vcpu *vcpu)
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{
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struct kvm_vcpu_timer *t = &vcpu->arch.timer;
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struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
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u64 delta_ns;
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if (!t->init_done)
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return;
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delta_ns = kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t);
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if (delta_ns) {
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hrtimer_start(&t->hrt, ktime_set(0, delta_ns), HRTIMER_MODE_REL);
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t->next_set = true;
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}
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}
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static void kvm_riscv_vcpu_timer_unblocking(struct kvm_vcpu *vcpu)
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{
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kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
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}
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int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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struct kvm_vcpu_timer *t = &vcpu->arch.timer;
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struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
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u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_TIMER);
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u64 reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(u64))
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return -EINVAL;
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if (reg_num >= sizeof(struct kvm_riscv_timer) / sizeof(u64))
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return -EINVAL;
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switch (reg_num) {
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case KVM_REG_RISCV_TIMER_REG(frequency):
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reg_val = riscv_timebase;
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break;
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case KVM_REG_RISCV_TIMER_REG(time):
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reg_val = kvm_riscv_current_cycles(gt);
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break;
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case KVM_REG_RISCV_TIMER_REG(compare):
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reg_val = t->next_cycles;
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break;
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case KVM_REG_RISCV_TIMER_REG(state):
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reg_val = (t->next_set) ? KVM_RISCV_TIMER_STATE_ON :
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KVM_RISCV_TIMER_STATE_OFF;
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break;
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default:
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return -EINVAL;
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}
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if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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return 0;
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}
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int kvm_riscv_vcpu_set_reg_timer(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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struct kvm_vcpu_timer *t = &vcpu->arch.timer;
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struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
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u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_TIMER);
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u64 reg_val;
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int ret = 0;
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if (KVM_REG_SIZE(reg->id) != sizeof(u64))
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return -EINVAL;
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if (reg_num >= sizeof(struct kvm_riscv_timer) / sizeof(u64))
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return -EINVAL;
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if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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switch (reg_num) {
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case KVM_REG_RISCV_TIMER_REG(frequency):
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ret = -EOPNOTSUPP;
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break;
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case KVM_REG_RISCV_TIMER_REG(time):
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gt->time_delta = reg_val - get_cycles64();
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break;
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case KVM_REG_RISCV_TIMER_REG(compare):
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t->next_cycles = reg_val;
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break;
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case KVM_REG_RISCV_TIMER_REG(state):
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if (reg_val == KVM_RISCV_TIMER_STATE_ON)
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ret = kvm_riscv_vcpu_timer_next_event(vcpu, reg_val);
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else
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ret = kvm_riscv_vcpu_timer_cancel(t);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu)
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{
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struct kvm_vcpu_timer *t = &vcpu->arch.timer;
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if (t->init_done)
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return -EINVAL;
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hrtimer_init(&t->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
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t->init_done = true;
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t->next_set = false;
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/* Enable sstc for every vcpu if available in hardware */
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if (riscv_isa_extension_available(NULL, SSTC)) {
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t->sstc_enabled = true;
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t->hrt.function = kvm_riscv_vcpu_vstimer_expired;
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t->timer_next_event = kvm_riscv_vcpu_update_vstimecmp;
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} else {
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t->sstc_enabled = false;
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t->hrt.function = kvm_riscv_vcpu_hrtimer_expired;
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t->timer_next_event = kvm_riscv_vcpu_update_hrtimer;
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}
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return 0;
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}
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int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu)
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{
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int ret;
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ret = kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
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vcpu->arch.timer.init_done = false;
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return ret;
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}
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int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu)
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{
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struct kvm_vcpu_timer *t = &vcpu->arch.timer;
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t->next_cycles = -1ULL;
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return kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
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}
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static void kvm_riscv_vcpu_update_timedelta(struct kvm_vcpu *vcpu)
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{
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struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
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#if defined(CONFIG_32BIT)
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csr_write(CSR_HTIMEDELTA, (u32)(gt->time_delta));
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csr_write(CSR_HTIMEDELTAH, (u32)(gt->time_delta >> 32));
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#else
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csr_write(CSR_HTIMEDELTA, gt->time_delta);
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#endif
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}
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void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
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{
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struct kvm_vcpu_csr *csr;
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struct kvm_vcpu_timer *t = &vcpu->arch.timer;
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kvm_riscv_vcpu_update_timedelta(vcpu);
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if (!t->sstc_enabled)
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return;
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csr = &vcpu->arch.guest_csr;
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#if defined(CONFIG_32BIT)
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csr_write(CSR_VSTIMECMP, (u32)t->next_cycles);
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csr_write(CSR_VSTIMECMPH, (u32)(t->next_cycles >> 32));
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#else
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csr_write(CSR_VSTIMECMP, t->next_cycles);
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#endif
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/* timer should be enabled for the remaining operations */
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if (unlikely(!t->init_done))
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return;
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kvm_riscv_vcpu_timer_unblocking(vcpu);
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}
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void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu)
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{
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struct kvm_vcpu_csr *csr;
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struct kvm_vcpu_timer *t = &vcpu->arch.timer;
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if (!t->sstc_enabled)
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return;
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csr = &vcpu->arch.guest_csr;
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t = &vcpu->arch.timer;
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#if defined(CONFIG_32BIT)
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t->next_cycles = csr_read(CSR_VSTIMECMP);
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t->next_cycles |= (u64)csr_read(CSR_VSTIMECMPH) << 32;
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#else
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t->next_cycles = csr_read(CSR_VSTIMECMP);
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#endif
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/* timer should be enabled for the remaining operations */
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if (unlikely(!t->init_done))
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return;
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if (kvm_vcpu_is_blocking(vcpu))
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kvm_riscv_vcpu_timer_blocking(vcpu);
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}
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void kvm_riscv_guest_timer_init(struct kvm *kvm)
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{
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struct kvm_guest_timer *gt = &kvm->arch.timer;
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riscv_cs_get_mult_shift(>->nsec_mult, >->nsec_shift);
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gt->time_delta = -get_cycles64();
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}
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