Adjust removal control flow for smu v13_0_2: During amdgpu uninstallation, when removing the first device, the kernel needs to first send a mode1reset message to all gpu devices. Otherwise, smu initialization will fail the next time amdgpu is installed. V2: 1. Update commit comments. 2. Remove the global variable amdgpu_device_remove_cnt and add a variable to the structure amdgpu_hive_info. 3. Use hive to detect the first removed device instead of a global variable. V3: 1. Update commit comments. 2. Split a patch into multiple patches. 3. The current patch does: a. Add a work mode of AMDGPU_RESET_FOR_DEVICE_REMOVE into the existing gpu recover path, which make all devices in hive list only have HW reset but no resume (except the base IP). b. Call AMDGPU_RESET_FOR_DEVICE_REMOVE and AMDGPU_NEED_FULL_RESET mode of amdgpu_device_gpu_recover in amdgpu_pci_remove when removing the first device in hive list. c. When removing the first device, the IP blocks keyword function call sequence is as follows: .suspend->mode1reset->.resume(basic ip)->.hw_fini->.early_fini->.sw_fini. ^ | |-<----------<---------<----| The first three sequences are because of a call to amdgpu_device_gpu_recover. The three sequences will be executed in a loop until all devices in the hive list are iterated. The sequences starting from .hw_fini only apply to the first device. Since .suspend has been called before, except the resumed phase1 basic ip blocks, all other ip blocks .hw_fini of current device will do nothing. d. When removing other devices, the calling sequences is the same as legacy: .hw_fini -> .early_fini -> .sw_fini. Since .suspend has been called when removing the first device, except the resumed phase1 basic ip blocks, all of other ip blocks .hw_fini of current device will do nothing. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
129 lines
4.1 KiB
C
129 lines
4.1 KiB
C
/*
|
|
* Copyright 2021 Advanced Micro Devices, Inc.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
* OTHER DEALINGS IN THE SOFTWARE.
|
|
*
|
|
*/
|
|
|
|
#ifndef __AMDGPU_RESET_H__
|
|
#define __AMDGPU_RESET_H__
|
|
|
|
#include "amdgpu.h"
|
|
|
|
enum AMDGPU_RESET_FLAGS {
|
|
|
|
AMDGPU_NEED_FULL_RESET = 0,
|
|
AMDGPU_SKIP_HW_RESET = 1,
|
|
AMDGPU_SKIP_MODE2_RESET = 2,
|
|
AMDGPU_RESET_FOR_DEVICE_REMOVE = 3,
|
|
};
|
|
|
|
struct amdgpu_reset_context {
|
|
enum amd_reset_method method;
|
|
struct amdgpu_device *reset_req_dev;
|
|
struct amdgpu_job *job;
|
|
struct amdgpu_hive_info *hive;
|
|
struct list_head *reset_device_list;
|
|
unsigned long flags;
|
|
};
|
|
|
|
struct amdgpu_reset_handler {
|
|
enum amd_reset_method reset_method;
|
|
struct list_head handler_list;
|
|
int (*prepare_env)(struct amdgpu_reset_control *reset_ctl,
|
|
struct amdgpu_reset_context *context);
|
|
int (*prepare_hwcontext)(struct amdgpu_reset_control *reset_ctl,
|
|
struct amdgpu_reset_context *context);
|
|
int (*perform_reset)(struct amdgpu_reset_control *reset_ctl,
|
|
struct amdgpu_reset_context *context);
|
|
int (*restore_hwcontext)(struct amdgpu_reset_control *reset_ctl,
|
|
struct amdgpu_reset_context *context);
|
|
int (*restore_env)(struct amdgpu_reset_control *reset_ctl,
|
|
struct amdgpu_reset_context *context);
|
|
|
|
int (*do_reset)(struct amdgpu_device *adev);
|
|
};
|
|
|
|
struct amdgpu_reset_control {
|
|
void *handle;
|
|
struct work_struct reset_work;
|
|
struct mutex reset_lock;
|
|
struct list_head reset_handlers;
|
|
atomic_t in_reset;
|
|
enum amd_reset_method active_reset;
|
|
struct amdgpu_reset_handler *(*get_reset_handler)(
|
|
struct amdgpu_reset_control *reset_ctl,
|
|
struct amdgpu_reset_context *context);
|
|
void (*async_reset)(struct work_struct *work);
|
|
};
|
|
|
|
|
|
enum amdgpu_reset_domain_type {
|
|
SINGLE_DEVICE,
|
|
XGMI_HIVE
|
|
};
|
|
|
|
struct amdgpu_reset_domain {
|
|
struct kref refcount;
|
|
struct workqueue_struct *wq;
|
|
enum amdgpu_reset_domain_type type;
|
|
struct rw_semaphore sem;
|
|
atomic_t in_gpu_reset;
|
|
atomic_t reset_res;
|
|
};
|
|
|
|
|
|
int amdgpu_reset_init(struct amdgpu_device *adev);
|
|
int amdgpu_reset_fini(struct amdgpu_device *adev);
|
|
|
|
int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
|
|
struct amdgpu_reset_context *reset_context);
|
|
|
|
int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
|
|
struct amdgpu_reset_context *reset_context);
|
|
|
|
int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
|
|
struct amdgpu_reset_handler *handler);
|
|
|
|
struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
|
|
char *wq_name);
|
|
|
|
void amdgpu_reset_destroy_reset_domain(struct kref *ref);
|
|
|
|
static inline bool amdgpu_reset_get_reset_domain(struct amdgpu_reset_domain *domain)
|
|
{
|
|
return kref_get_unless_zero(&domain->refcount) != 0;
|
|
}
|
|
|
|
static inline void amdgpu_reset_put_reset_domain(struct amdgpu_reset_domain *domain)
|
|
{
|
|
kref_put(&domain->refcount, amdgpu_reset_destroy_reset_domain);
|
|
}
|
|
|
|
static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *domain,
|
|
struct work_struct *work)
|
|
{
|
|
return queue_work(domain->wq, work);
|
|
}
|
|
|
|
void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain);
|
|
|
|
void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain);
|
|
|
|
#endif
|