6651875ad7
[Why] PSR-SU Rate Control - or PSR-SU-RC - enables PSR-SU panels to work with variable refresh rate to allow for more power savings. Lowering the refresh rate can increase PSR residency by expanding the eDP main link shut down duration. It can also lower panel power consumption. There is a complication with PSR, since the eDP main link can be shut down. Therefore, the timing controller (TCON) on the eDP sink nees to be able to scan out its remote buffer independent of the main link. To allow the eDP source to specify the sink's refresh rate while the link is off, vendor-specific DPCD registers are used. This allows the eDP source to then "Rate Control" the panel during PSR active. [How] Add DC support to communicate with PSR-SU-RC supported eDP sinks. The sink will need to know the desired VTotal during PSR active. This change only adds support to DC, support in amdgpu_dm is still pending to enable this fully. Signed-off-by: David Zhang <dingchen.zhang@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
58 lines
2.2 KiB
C
58 lines
2.2 KiB
C
/*
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* Copyright 2012-16 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef _DMUB_PSR_H_
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#define _DMUB_PSR_H_
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#include "os_types.h"
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#include "dc_link.h"
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struct dmub_psr {
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struct dc_context *ctx;
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const struct dmub_psr_funcs *funcs;
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};
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struct dmub_psr_funcs {
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bool (*psr_copy_settings)(struct dmub_psr *dmub, struct dc_link *link,
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struct psr_context *psr_context, uint8_t panel_inst);
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void (*psr_enable)(struct dmub_psr *dmub, bool enable, bool wait,
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uint8_t panel_inst);
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void (*psr_get_state)(struct dmub_psr *dmub, enum dc_psr_state *dc_psr_state,
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uint8_t panel_inst);
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void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level,
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uint8_t panel_inst);
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void (*psr_force_static)(struct dmub_psr *dmub, uint8_t panel_inst);
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void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency,
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uint8_t panel_inst);
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void (*psr_set_sink_vtotal_in_psr_active)(struct dmub_psr *dmub,
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uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);
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void (*psr_set_power_opt)(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst);
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};
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struct dmub_psr *dmub_psr_create(struct dc_context *ctx);
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void dmub_psr_destroy(struct dmub_psr **dmub);
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#endif /* _DMUB_PSR_H_ */
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