6290ba4c16
In order to handle FPO correctly, we need to reinstate the dram values. This function adds the required code to handle the vblank stretch and the dram calculation. Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
107 lines
3.6 KiB
C
107 lines
3.6 KiB
C
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef _DCN30_RESOURCE_H_
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#define _DCN30_RESOURCE_H_
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#include "core_types.h"
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#define TO_DCN30_RES_POOL(pool)\
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container_of(pool, struct dcn30_resource_pool, base)
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struct dc;
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struct resource_pool;
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struct _vcs_dpi_display_pipe_params_st;
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extern struct _vcs_dpi_ip_params_st dcn3_0_ip;
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extern struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc;
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struct dcn30_resource_pool {
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struct resource_pool base;
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};
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struct resource_pool *dcn30_create_resource_pool(
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const struct dc_init_data *init_data,
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struct dc *dc);
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void dcn30_set_mcif_arb_params(
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struct dc *dc,
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struct dc_state *context,
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display_e2e_pipe_params_st *pipes,
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int pipe_cnt);
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unsigned int dcn30_calc_max_scaled_time(
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unsigned int time_per_pixel,
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enum mmhubbub_wbif_mode mode,
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unsigned int urgent_watermark);
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bool dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,
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bool fast_validate);
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bool dcn30_internal_validate_bw(
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struct dc *dc,
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struct dc_state *context,
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display_e2e_pipe_params_st *pipes,
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int *pipe_cnt_out,
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int *vlevel_out,
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bool fast_validate);
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void dcn30_calculate_wm_and_dlg(
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struct dc *dc, struct dc_state *context,
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display_e2e_pipe_params_st *pipes,
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int pipe_cnt,
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int vlevel);
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void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
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void dcn30_populate_dml_writeback_from_context(
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struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
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int dcn30_populate_dml_pipes_from_context(
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struct dc *dc, struct dc_state *context,
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display_e2e_pipe_params_st *pipes,
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bool fast_validate);
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bool dcn30_acquire_post_bldn_3dlut(
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struct resource_context *res_ctx,
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const struct resource_pool *pool,
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int mpcc_id,
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struct dc_3dlut **lut,
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struct dc_transfer_func **shaper);
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bool dcn30_release_post_bldn_3dlut(
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struct resource_context *res_ctx,
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const struct resource_pool *pool,
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struct dc_3dlut **lut,
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struct dc_transfer_func **shaper);
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enum dc_status dcn30_add_stream_to_ctx(
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struct dc *dc,
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struct dc_state *new_ctx,
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struct dc_stream_state *dc_stream);
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void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);
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void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);
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int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context,
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display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
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#endif /* _DCN30_RESOURCE_H_ */
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