9c75891fee
[why] Original change594b237b9a("drm/amd/display: Add interface to track PHY state") was implemented by assuming stream's dpms off is equivalent to PHY power off. This assumption doesn't hold in following situations: 1. MST multiple stream scenario, where multiple streams are sharing the same PHY output. Toggle dpms off for one of the stream doesn't power off the PHY due to the presence of other streams. 2. enable stream failure scenario, where enable stream fails due to failure of link training. This will cause DPMS off is set to false, while the actual PHY power state is off in certain cases. Due to the problematic assumption, the logic will skip disabling other streams for MST multiple stream scenario, therefore PHY is not actually powered off. [how] 1. Rework this refactor by moving PHY state update down to hardware level, where we update PHY state in place when hardware sequencer is actually changing the power state of the PHY hardware. 2. Reimplement symclk on TX off workaround in place when we are actually calling transmitter control to power off PHY in dcn32. Note the workaround is added due to the lack of proper software interface to set TX while keeping symclk on. We plan to address this interface problem so we can set TX off only without affecting symclk in future dcn versions. Fixes:594b237b9a("drm/amd/display: Add interface to track PHY state") Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
95 lines
3.2 KiB
C
95 lines
3.2 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_HWSS_DCN32_H__
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#define __DC_HWSS_DCN32_H__
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#include "hw_sequencer_private.h"
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struct dc;
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void dcn32_dsc_pg_control(
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struct dce_hwseq *hws,
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unsigned int dsc_inst,
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bool power_on);
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void dcn32_enable_power_gating_plane(
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struct dce_hwseq *hws,
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bool enable);
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void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
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bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
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void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
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void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
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bool dcn32_set_mcm_luts(struct pipe_ctx *pipe_ctx,
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const struct dc_plane_state *plane_state);
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bool dcn32_set_input_transfer_func(struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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const struct dc_plane_state *plane_state);
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bool dcn32_set_output_transfer_func(struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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const struct dc_stream_state *stream);
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void dcn32_init_hw(struct dc *dc);
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void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
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void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
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void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context);
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void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
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unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
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void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
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void dcn32_subvp_pipe_control_lock(struct dc *dc,
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struct dc_state *context,
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bool lock,
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bool should_lock_all_pipes,
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struct pipe_ctx *top_pipe_to_program,
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bool subvp_prev_use);
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void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
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struct dc_link_settings *link_settings);
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bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
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void dcn32_disable_link_output(struct dc_link *link,
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const struct link_resource *link_res,
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enum signal_type signal);
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void dcn32_update_phantom_vp_position(struct dc *dc,
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struct dc_state *context,
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struct pipe_ctx *phantom_pipe);
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#endif /* __DC_HWSS_DCN32_H__ */
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