Mauro Rossi 61bf32937b drm/amd/display: dc/irq: add support for DCE6 (v4) ... [Why] irq service requires changes for DCE6 support [How] (v1) DCE6 targets are added replicating existing DCE8 implementation. due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks, dce/dce_8_0_{d,sh_mask}.h used instead of dce/dce_6_0_{d,sh_mask}.h (v2) DCE6 headers used adding the necessary vblank irq registers (INT_MASK and VBLANK_STATUS) and vblank irq masks as implemented in amdgpu driver. Add vblank_irq_info_funcs_dce60 with .set and .ack as per commit b10d51f ("drm/amd/display: Add interrupt entries for VBLANK isr.") and use it in vblank_int_entry(reg_num) macro definition (v3) updated due to following kernel 5.3 commit: 4fc4dca ("drm/amd: drop use of drmp.h in os_types.h") (v4) updated due to following kernel 5.6 commit: d9e3267 ("drm/amd/display: cleanup of construct and destruct funcs") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-07-27 16:46:02 -04:00
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irq_service_dce60.c	drm/amd/display: dc/irq: add support for DCE6 (v4)	2020-07-27 16:46:02 -04:00
irq_service_dce60.h	drm/amd/display: dc/irq: add support for DCE6 (v4)	2020-07-27 16:46:02 -04:00