307f049bfc
This pacth is to add the parameters of power profiles for vangogh, includeing "profile_peak", "profile_standard", "profile_min_sclk", "profile_min_mclk". Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
59 lines
2.4 KiB
C
59 lines
2.4 KiB
C
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __VANGOGH_PPT_H__
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#define __VANGOGH_PPT_H__
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extern void vangogh_set_ppt_funcs(struct smu_context *smu);
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/* UMD PState Vangogh Msg Parameters in MHz */
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#define VANGOGH_UMD_PSTATE_STANDARD_GFXCLK 1100
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#define VANGOGH_UMD_PSTATE_STANDARD_SOCCLK 600
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#define VANGOGH_UMD_PSTATE_STANDARD_FCLK 800
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#define VANGOGH_UMD_PSTATE_STANDARD_VCLK 705
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#define VANGOGH_UMD_PSTATE_STANDARD_DCLK 600
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#define VANGOGH_UMD_PSTATE_PEAK_GFXCLK 1300
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#define VANGOGH_UMD_PSTATE_PEAK_SOCCLK 600
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#define VANGOGH_UMD_PSTATE_PEAK_FCLK 800
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#define VANGOGH_UMD_PSTATE_PEAK_VCLK 705
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#define VANGOGH_UMD_PSTATE_PEAK_DCLK 600
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#define VANGOGH_UMD_PSTATE_MIN_SCLK_GFXCLK 400
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#define VANGOGH_UMD_PSTATE_MIN_SCLK_SOCCLK 1000
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#define VANGOGH_UMD_PSTATE_MIN_SCLK_FCLK 800
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#define VANGOGH_UMD_PSTATE_MIN_SCLK_VCLK 1000
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#define VANGOGH_UMD_PSTATE_MIN_SCLK_DCLK 800
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#define VANGOGH_UMD_PSTATE_MIN_MCLK_GFXCLK 1100
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#define VANGOGH_UMD_PSTATE_MIN_MCLK_SOCCLK 1000
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#define VANGOGH_UMD_PSTATE_MIN_MCLK_FCLK 400
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#define VANGOGH_UMD_PSTATE_MIN_MCLK_VCLK 1000
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#define VANGOGH_UMD_PSTATE_MIN_MCLK_DCLK 800
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/* RLC Power Status */
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#define RLC_STATUS_OFF 0
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#define RLC_STATUS_NORMAL 1
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#endif
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