b5917a109f
GSC requires more operational memory than available on chip. Reserve 4M of LMEM for GSC operation. The memory is provided to the GSC as struct resource to the auxiliary data of the child device. Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907215113.1596567-16-tomas.winkler@intel.com Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
40 lines
1,005 B
C
40 lines
1,005 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
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*/
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#ifndef __INTEL_GSC_DEV_H__
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#define __INTEL_GSC_DEV_H__
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#include <linux/types.h>
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struct drm_i915_private;
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struct intel_gt;
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struct mei_aux_device;
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#define INTEL_GSC_NUM_INTERFACES 2
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/*
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* The HECI1 bit corresponds to bit15 and HECI2 to bit14.
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* The reason for this is to allow growth for more interfaces in the future.
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*/
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#define GSC_IRQ_INTF(_x) BIT(15 - (_x))
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/**
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* struct intel_gsc - graphics security controller
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*
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* @gem_obj: scratch memory GSC operations
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* @intf : gsc interface
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*/
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struct intel_gsc {
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struct intel_gsc_intf {
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struct mei_aux_device *adev;
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struct drm_i915_gem_object *gem_obj;
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int irq;
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unsigned int id;
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} intf[INTEL_GSC_NUM_INTERFACES];
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};
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void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *dev_priv);
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void intel_gsc_fini(struct intel_gsc *gsc);
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void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir);
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#endif /* __INTEL_GSC_DEV_H__ */
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