9a92732f04
Although all DSS belong to a single pool on Xe_HP platforms (i.e., they're not organized into slices from a topology point of view), we do still need to pass 'group' and 'instance' targets when steering register accesses to a specific instance of a per-DSS multicast register. The rules for how to determine group and instance IDs (which previously used legacy terms "slice" and "subslice") varies by platform. Some platforms determine steering by gslice membership, some platforms by cslice membership, and future platforms may have other rules. Since looping over each DSS and performing steered unicast register accesses is a relatively common pattern, let's add a dedicated iteration macro to handle this (and replace the platform-specific "instdone" loop we were using previously. This will avoid the calling code needing to figure out the details about how to obtain steering IDs for a specific DSS. Most of the places where we use this new loop are in the GPU errorstate code at the moment, but we do have some additional features coming in the future that will also need to loop over each DSS and steer some register accesses accordingly. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220701232006.1016135-1-matthew.d.roper@intel.com
58 lines
2 KiB
C
58 lines
2 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __INTEL_GT_MCR__
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#define __INTEL_GT_MCR__
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#include "intel_gt_types.h"
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void intel_gt_mcr_init(struct intel_gt *gt);
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u32 intel_gt_mcr_read(struct intel_gt *gt,
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i915_reg_t reg,
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int group, int instance);
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u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg);
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u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg);
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void intel_gt_mcr_unicast_write(struct intel_gt *gt,
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i915_reg_t reg, u32 value,
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int group, int instance);
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void intel_gt_mcr_multicast_write(struct intel_gt *gt,
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i915_reg_t reg, u32 value);
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void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt,
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i915_reg_t reg, u32 value);
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void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt,
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i915_reg_t reg,
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u8 *group, u8 *instance);
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void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
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bool dump_table);
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void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
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unsigned int *group, unsigned int *instance);
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/*
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* Helper for for_each_ss_steering loop. On pre-Xe_HP platforms, subslice
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* presence is determined by using the group/instance as direct lookups in the
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* slice/subslice topology. On Xe_HP and beyond, the steering is unrelated to
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* the topology, so we lookup the DSS ID directly in "slice 0."
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*/
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#define _HAS_SS(ss_, gt_, group_, instance_) ( \
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GRAPHICS_VER_FULL(gt_->i915) >= IP_VER(12, 50) ? \
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intel_sseu_has_subslice(&(gt_)->info.sseu, 0, ss_) : \
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intel_sseu_has_subslice(&(gt_)->info.sseu, group_, instance_))
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/*
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* Loop over each subslice/DSS and determine the group and instance IDs that
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* should be used to steer MCR accesses toward this DSS.
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*/
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#define for_each_ss_steering(ss_, gt_, group_, instance_) \
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for (ss_ = 0, intel_gt_mcr_get_ss_steering(gt_, 0, &group_, &instance_); \
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ss_ < I915_MAX_SS_FUSE_BITS; \
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ss_++, intel_gt_mcr_get_ss_steering(gt_, ss_, &group_, &instance_)) \
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for_each_if(_HAS_SS(ss_, gt_, group_, instance_))
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#endif /* __INTEL_GT_MCR__ */
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