PVC also has a hwconfig table. Actually the current expectation is that all future platforms will have hwconfig, so let's just change the condition to an IP version check so that we don't need to keep updating this for each new platform that shows up. Cc: John Harrison <john.c.harrison@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220524235906.529771-1-matthew.d.roper@intel.com
164 lines
3.4 KiB
C
164 lines
3.4 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "gt/intel_gt.h"
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#include "gt/intel_hwconfig.h"
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#include "i915_drv.h"
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#include "i915_memcpy.h"
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/*
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* GuC has a blob containing hardware configuration information (HWConfig).
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* This is formatted as a simple and flexible KLV (Key/Length/Value) table.
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*
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* For example, a minimal version could be:
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* enum device_attr {
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* ATTR_SOME_VALUE = 0,
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* ATTR_SOME_MASK = 1,
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* };
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*
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* static const u32 hwconfig[] = {
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* ATTR_SOME_VALUE,
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* 1, // Value Length in DWords
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* 8, // Value
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*
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* ATTR_SOME_MASK,
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* 3,
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* 0x00FFFFFFFF, 0xFFFFFFFF, 0xFF000000,
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* };
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*
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* The attribute ids are defined in a hardware spec.
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*/
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static int __guc_action_get_hwconfig(struct intel_guc *guc,
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u32 ggtt_offset, u32 ggtt_size)
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{
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u32 action[] = {
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INTEL_GUC_ACTION_GET_HWCONFIG,
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lower_32_bits(ggtt_offset),
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upper_32_bits(ggtt_offset),
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ggtt_size,
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};
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int ret;
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ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
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if (ret == -ENXIO)
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return -ENOENT;
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return ret;
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}
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static int guc_hwconfig_discover_size(struct intel_guc *guc, struct intel_hwconfig *hwconfig)
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{
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int ret;
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/*
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* Sending a query with zero offset and size will return the
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* size of the blob.
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*/
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ret = __guc_action_get_hwconfig(guc, 0, 0);
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if (ret < 0)
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return ret;
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if (ret == 0)
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return -EINVAL;
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hwconfig->size = ret;
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return 0;
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}
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static int guc_hwconfig_fill_buffer(struct intel_guc *guc, struct intel_hwconfig *hwconfig)
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{
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struct i915_vma *vma;
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u32 ggtt_offset;
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void *vaddr;
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int ret;
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GEM_BUG_ON(!hwconfig->size);
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ret = intel_guc_allocate_and_map_vma(guc, hwconfig->size, &vma, &vaddr);
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if (ret)
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return ret;
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ggtt_offset = intel_guc_ggtt_offset(guc, vma);
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ret = __guc_action_get_hwconfig(guc, ggtt_offset, hwconfig->size);
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if (ret >= 0)
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memcpy(hwconfig->ptr, vaddr, hwconfig->size);
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i915_vma_unpin_and_release(&vma, I915_VMA_RELEASE_MAP);
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return ret;
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}
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static bool has_table(struct drm_i915_private *i915)
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{
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if (IS_ALDERLAKE_P(i915) && !IS_ADLP_N(i915))
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return true;
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if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
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return true;
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return false;
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}
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/**
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* intel_guc_hwconfig_init - Initialize the HWConfig
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*
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* Retrieve the HWConfig table from the GuC and save it locally.
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* It can then be queried on demand by other users later on.
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*/
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static int guc_hwconfig_init(struct intel_gt *gt)
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{
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struct intel_hwconfig *hwconfig = >->info.hwconfig;
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struct intel_guc *guc = >->uc.guc;
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int ret;
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if (!has_table(gt->i915))
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return 0;
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ret = guc_hwconfig_discover_size(guc, hwconfig);
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if (ret)
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return ret;
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hwconfig->ptr = kmalloc(hwconfig->size, GFP_KERNEL);
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if (!hwconfig->ptr) {
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hwconfig->size = 0;
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return -ENOMEM;
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}
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ret = guc_hwconfig_fill_buffer(guc, hwconfig);
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if (ret < 0) {
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intel_gt_fini_hwconfig(gt);
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return ret;
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}
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return 0;
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}
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/**
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* intel_gt_init_hwconfig - Initialize the HWConfig if available
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*
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* Retrieve the HWConfig table if available on the current platform.
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*/
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int intel_gt_init_hwconfig(struct intel_gt *gt)
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{
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if (!intel_uc_uses_guc(>->uc))
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return 0;
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return guc_hwconfig_init(gt);
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}
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/**
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* intel_gt_fini_hwconfig - Finalize the HWConfig
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*
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* Free up the memory allocation holding the table.
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*/
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void intel_gt_fini_hwconfig(struct intel_gt *gt)
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{
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struct intel_hwconfig *hwconfig = >->info.hwconfig;
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kfree(hwconfig->ptr);
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hwconfig->size = 0;
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hwconfig->ptr = NULL;
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}
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