4f128f8e1a
Add Stage-2 mmu data structures for virtual EL2 and for nested guests. We don't yet populate shadow Stage-2 page tables, but we now have a framework for getting to a shadow Stage-2 pgd. We allocate twice the number of vcpus as Stage-2 mmu structures because that's sufficient for each vcpu running two translation regimes without having to flush the Stage-2 page tables. Co-developed-by: Christoffer Dall <christoffer.dall@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20240614144552.2773592-2-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
85 lines
2.3 KiB
C
85 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ARM64_KVM_NESTED_H
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#define __ARM64_KVM_NESTED_H
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#include <linux/bitfield.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_emulate.h>
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static inline bool vcpu_has_nv(const struct kvm_vcpu *vcpu)
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{
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return (!__is_defined(__KVM_NVHE_HYPERVISOR__) &&
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cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) &&
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vcpu_has_feature(vcpu, KVM_ARM_VCPU_HAS_EL2));
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}
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/* Translation helpers from non-VHE EL2 to EL1 */
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static inline u64 tcr_el2_ps_to_tcr_el1_ips(u64 tcr_el2)
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{
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return (u64)FIELD_GET(TCR_EL2_PS_MASK, tcr_el2) << TCR_IPS_SHIFT;
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}
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static inline u64 translate_tcr_el2_to_tcr_el1(u64 tcr)
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{
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return TCR_EPD1_MASK | /* disable TTBR1_EL1 */
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((tcr & TCR_EL2_TBI) ? TCR_TBI0 : 0) |
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tcr_el2_ps_to_tcr_el1_ips(tcr) |
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(tcr & TCR_EL2_TG0_MASK) |
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(tcr & TCR_EL2_ORGN0_MASK) |
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(tcr & TCR_EL2_IRGN0_MASK) |
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(tcr & TCR_EL2_T0SZ_MASK);
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}
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static inline u64 translate_cptr_el2_to_cpacr_el1(u64 cptr_el2)
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{
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u64 cpacr_el1 = 0;
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if (cptr_el2 & CPTR_EL2_TTA)
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cpacr_el1 |= CPACR_ELx_TTA;
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if (!(cptr_el2 & CPTR_EL2_TFP))
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cpacr_el1 |= CPACR_ELx_FPEN;
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if (!(cptr_el2 & CPTR_EL2_TZ))
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cpacr_el1 |= CPACR_ELx_ZEN;
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return cpacr_el1;
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}
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static inline u64 translate_sctlr_el2_to_sctlr_el1(u64 val)
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{
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/* Only preserve the minimal set of bits we support */
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val &= (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | SCTLR_ELx_SA |
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SCTLR_ELx_I | SCTLR_ELx_IESB | SCTLR_ELx_WXN | SCTLR_ELx_EE);
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val |= SCTLR_EL1_RES1;
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return val;
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}
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static inline u64 translate_ttbr0_el2_to_ttbr0_el1(u64 ttbr0)
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{
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/* Clear the ASID field */
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return ttbr0 & ~GENMASK_ULL(63, 48);
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}
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extern bool forward_smc_trap(struct kvm_vcpu *vcpu);
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extern void kvm_init_nested(struct kvm *kvm);
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extern int kvm_vcpu_init_nested(struct kvm_vcpu *vcpu);
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extern void kvm_init_nested_s2_mmu(struct kvm_s2_mmu *mmu);
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extern struct kvm_s2_mmu *lookup_s2_mmu(struct kvm_vcpu *vcpu);
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extern void kvm_vcpu_load_hw_mmu(struct kvm_vcpu *vcpu);
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extern void kvm_vcpu_put_hw_mmu(struct kvm_vcpu *vcpu);
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int kvm_init_nv_sysregs(struct kvm *kvm);
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#ifdef CONFIG_ARM64_PTR_AUTH
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bool kvm_auth_eretax(struct kvm_vcpu *vcpu, u64 *elr);
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#else
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static inline bool kvm_auth_eretax(struct kvm_vcpu *vcpu, u64 *elr)
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{
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/* We really should never execute this... */
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WARN_ON_ONCE(1);
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*elr = 0xbad9acc0debadbad;
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return false;
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}
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#endif
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#endif /* __ARM64_KVM_NESTED_H */
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