d14bc28af3
Add RX lane margining settings for 16.0 GT/s (GEN 4) data rate. These settings improve link stability while operating at high date rates and helps to improve signal quality. Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-4-743f5c1fd027@linaro.org Tested-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com> [mani: dropped the code refactoring and minor changes] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
78 lines
2.8 KiB
C
78 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/pci.h>
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#include "pcie-designware.h"
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#include "pcie-qcom-common.h"
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void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci)
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{
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u32 reg;
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/*
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* GEN3_RELATED_OFF register is repurposed to apply equalization
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* settings at various data transmission rates through registers namely
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* GEN3_EQ_*. The RATE_SHADOW_SEL bit field of GEN3_RELATED_OFF
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* determines the data rate for which these equalization settings are
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* applied.
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*/
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reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
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reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
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reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
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reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK,
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GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT);
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dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg);
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reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF);
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reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 |
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GEN3_EQ_FMDC_N_EVALS |
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GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA |
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GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA);
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reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) |
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FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) |
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FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) |
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FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5);
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dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg);
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reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
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reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE |
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GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE |
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GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL |
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GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC);
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dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg);
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}
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EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_equalization);
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void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci)
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{
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u32 reg;
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reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF);
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reg &= ~(MARGINING_MAX_VOLTAGE_OFFSET |
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MARGINING_NUM_VOLTAGE_STEPS |
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MARGINING_MAX_TIMING_OFFSET |
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MARGINING_NUM_TIMING_STEPS);
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reg |= FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) |
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FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) |
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FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) |
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FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10);
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dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg);
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reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF);
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reg |= MARGINING_IND_ERROR_SAMPLER |
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MARGINING_SAMPLE_REPORTING_METHOD |
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MARGINING_IND_LEFT_RIGHT_TIMING |
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MARGINING_VOLTAGE_SUPPORTED;
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reg &= ~(MARGINING_IND_UP_DOWN_VOLTAGE |
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MARGINING_MAXLANES |
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MARGINING_SAMPLE_RATE_TIMING |
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MARGINING_SAMPLE_RATE_VOLTAGE);
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reg |= FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) |
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FIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) |
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FIELD_PREP(MARGINING_SAMPLE_RATE_VOLTAGE, 0x3f);
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dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg);
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}
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EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_lane_margining);
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