e731f3146f
SoC changes, a substantial part of this is cleanup of some of the older
platforms that used to have a bunch of board files. In particular:
- Removal of non-DT i.MX platforms that haven't seen activity in years,
it's time to remove them.
- A bunch of cleanup and removal of platform data for TI/OMAP platforms,
moving over to genpd for power/reset control (yay!)
- Major cleanup of Samsung S3C24xx and S3C64xx platforms, moving them
closer to multiplatform support (not quite there yet, but getting
close).
THere are a few other changes too, smaller fixlets, etc. For new
platform support, the primary ones re:
- New SoC: Hisilicon SD5203, ARM926EJ-S platform.
- Cpufreq support for i.MX7ULP
-----BEGIN PGP SIGNATURE-----
iQJDBAABCgAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl+TT4gPHG9sb2ZAbGl4
b20ubmV0AAoJEIwa5zzehBx322MP/1mI56SyOFx30AqtWBPSjHJp+DzhOObyb4vD
ndYuicBIn9tJwvVRBBZkfsbIU8EENVwrN3hOpesaj9L7xiqOqKakcnyC1REYmpIs
8XBDfdZzy5PrMHIu3fF1ZDCQyO7KndGf5DfLVxJtcf1tSPQyQCuIA3FtS6d8Bxnz
r491+om67ucnlFD5X0Spm3RdZH+ECmXx2iXwoS0Zi7P+X+S+ovG8wBV/X0ggeoBc
Zgi4W01SiRupmSVZ6PA7FvWaLGQErQAALQOcFtMcFgjeWzc1v2QzcURELH8JW7ro
72AH9st1Kvi3hoN2HNNzUnNUdQvZ+AdH8skMIpN/e1cBYqYStAF3gm/R9h+iVHbG
GMmgzXHAFErfAW2UcF8tq1CzvQ5ChcTLNXdeoa8CeQbcDfocF3EyuKSPuDH+ve0H
kk4tPesTAc6XCEVwLaGnoC75sdum5mSi8h9vqhln2KCdeTY7jxzH9YGHjm71Supb
kV9vqo5Q5U/c5l2nU4r5q/DZdIahKsk3HIQZ0iG7BifAzamaTh4uyLVjtM6HSwNz
tdHZaxoHd/PLI5IoeggFelx6qgvK5qVRLP0evgOdTLRFLj/ZbrOf0Q7DjdTy2BjZ
Lgq461QqNapOzxq43G2IDT2+P62Q1+d+YLCKBgaGQaJicyU5m9STCNo3UBb1qH1h
W6UwGF5z
=0+Ee
-----END PGP SIGNATURE-----
Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC platform updates from Olof Johansson:
"SoC changes, a substantial part of this is cleanup of some of the
older platforms that used to have a bunch of board files.
In particular:
- Remove non-DT i.MX platforms that haven't seen activity in years,
it's time to remove them.
- A bunch of cleanup and removal of platform data for TI/OMAP
platforms, moving over to genpd for power/reset control (yay!)
- Major cleanup of Samsung S3C24xx and S3C64xx platforms, moving them
closer to multiplatform support (not quite there yet, but getting
close).
There are a few other changes too, smaller fixlets, etc. For new
platform support, the primary ones are:
- New SoC: Hisilicon SD5203, ARM926EJ-S platform.
- Cpufreq support for i.MX7ULP"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (121 commits)
ARM: mstar: Select MStar intc
ARM: stm32: Replace HTTP links with HTTPS ones
ARM: debug: add UART early console support for SD5203
ARM: hisi: add support for SD5203 SoC
ARM: omap3: enable off mode automatically
clk: imx: imx35: Remove mx35_clocks_init()
clk: imx: imx31: Remove mx31_clocks_init()
clk: imx: imx27: Remove mx27_clocks_init()
ARM: imx: Remove unused definitions
ARM: imx35: Retrieve the IIM base address from devicetree
ARM: imx3: Retrieve the AVIC base address from devicetree
ARM: imx3: Retrieve the CCM base address from devicetree
ARM: imx31: Retrieve the IIM base address from devicetree
ARM: imx27: Retrieve the CCM base address from devicetree
ARM: imx27: Retrieve the SYSCTRL base address from devicetree
ARM: s3c64xx: bring back notes from removed debug-macro.S
ARM: s3c24xx: fix Wunused-variable warning on !MMU
ARM: samsung: fix PM debug build with DEBUG_LL but !MMU
MAINTAINERS: mark linux-samsung-soc list non-moderated
ARM: imx: Remove remnant board file support pieces
...
180 lines
5.7 KiB
ArmAsm
180 lines
5.7 KiB
ArmAsm
/*
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* Copyright (C) 2016 Broadcom
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/serial_reg.h>
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#include <asm/cputype.h>
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/* Physical register offset and virtual register offset */
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#define REG_PHYS_BASE 0xf0000000
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#define REG_PHYS_BASE_V7 0x08000000
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#define REG_VIRT_BASE 0xfc000000
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#define REG_PHYS_ADDR(x) ((x) + REG_PHYS_BASE)
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#define REG_PHYS_ADDR_V7(x) ((x) + REG_PHYS_BASE_V7)
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/* Product id can be read from here */
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#define SUN_TOP_CTRL_BASE REG_PHYS_ADDR(0x404000)
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#define SUN_TOP_CTRL_BASE_V7 REG_PHYS_ADDR_V7(0x404000)
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#define UARTA_3390 REG_PHYS_ADDR(0x40a900)
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#define UARTA_7250 REG_PHYS_ADDR(0x40b400)
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#define UARTA_7255 REG_PHYS_ADDR(0x40c000)
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#define UARTA_7260 UARTA_7255
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#define UARTA_7268 UARTA_7255
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#define UARTA_7271 UARTA_7268
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#define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000)
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#define UARTA_7216 UARTA_7278
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#define UARTA_72164 UARTA_7278
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#define UARTA_72165 UARTA_7278
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#define UARTA_7364 REG_PHYS_ADDR(0x40b000)
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#define UARTA_7366 UARTA_7364
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#define UARTA_74371 REG_PHYS_ADDR(0x406b00)
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#define UARTA_7439 REG_PHYS_ADDR(0x40a900)
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#define UARTA_7445 REG_PHYS_ADDR(0x40ab00)
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#define UART_SHIFT 2
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#define checkuart(rp, rv, family_id, family) \
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/* Load family id */ \
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ldr rp, =family_id ; \
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/* Compare SUN_TOP_CTRL value against it */ \
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cmp rp, rv ; \
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/* Passed test, load address */ \
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ldreq rp, =UARTA_##family ; \
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/* Jump to save UART address */ \
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beq 91f
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.macro addruart, rp, rv, tmp
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adr \rp, 99f @ actual addr of 99f
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ldr \rv, [\rp] @ linked addr is stored there
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sub \rv, \rv, \rp @ offset between the two
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ldr \rp, [\rp, #4] @ linked brcmstb_uart_config
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sub \tmp, \rp, \rv @ actual brcmstb_uart_config
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ldr \rp, [\tmp] @ Load brcmstb_uart_config
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cmp \rp, #1 @ needs initialization?
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bne 100f @ no; go load the addresses
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mov \rv, #0 @ yes; record init is done
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str \rv, [\tmp]
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/* Check for V7 memory map if B53 */
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mrc p15, 0, \rv, c0, c0, 0 @ get Main ID register
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ldr \rp, =ARM_CPU_PART_MASK
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and \rv, \rv, \rp
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ldr \rp, =ARM_CPU_PART_BRAHMA_B53 @ check for B53 CPU
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cmp \rv, \rp
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bne 10f
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/* if PERIPHBASE doesn't overlap REG_PHYS_BASE use V7 map */
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mrc p15, 1, \rv, c15, c3, 0 @ get PERIPHBASE from CBAR
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ands \rv, \rv, #REG_PHYS_BASE
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ldreq \rp, =SUN_TOP_CTRL_BASE_V7
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/* Check SUN_TOP_CTRL base */
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10: ldrne \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA
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ldr \rv, [\rp, #0] @ get register contents
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ARM_BE8( rev \rv, \rv )
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and \rv, \rv, #0xffffff00 @ strip revision bits [7:0]
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/* Chip specific detection starts here */
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20: checkuart(\rp, \rv, 0x33900000, 3390)
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21: checkuart(\rp, \rv, 0x72160000, 7216)
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22: checkuart(\rp, \rv, 0x07216400, 72164)
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23: checkuart(\rp, \rv, 0x07216500, 72165)
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24: checkuart(\rp, \rv, 0x72500000, 7250)
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25: checkuart(\rp, \rv, 0x72550000, 7255)
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26: checkuart(\rp, \rv, 0x72600000, 7260)
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27: checkuart(\rp, \rv, 0x72680000, 7268)
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28: checkuart(\rp, \rv, 0x72710000, 7271)
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29: checkuart(\rp, \rv, 0x72780000, 7278)
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30: checkuart(\rp, \rv, 0x73640000, 7364)
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31: checkuart(\rp, \rv, 0x73660000, 7366)
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32: checkuart(\rp, \rv, 0x07437100, 74371)
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33: checkuart(\rp, \rv, 0x74390000, 7439)
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34: checkuart(\rp, \rv, 0x74450000, 7445)
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/* No valid UART found */
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90: mov \rp, #0
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/* fall through */
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/* Record whichever UART we chose */
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91: str \rp, [\tmp, #4] @ Store in brcmstb_uart_phys
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cmp \rp, #0 @ Valid UART address?
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bne 92f @ Yes, go process it
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str \rp, [\tmp, #8] @ Store 0 in brcmstb_uart_virt
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b 100f @ Done
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92: and \rv, \rp, #0xffffff @ offset within 16MB section
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add \rv, \rv, #REG_VIRT_BASE
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str \rv, [\tmp, #8] @ Store in brcmstb_uart_virt
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b 100f
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.align
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99: .word .
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.word brcmstb_uart_config
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.ltorg
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/* Load previously selected UART address */
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100: ldr \rp, [\tmp, #4] @ Load brcmstb_uart_phys
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ldr \rv, [\tmp, #8] @ Load brcmstb_uart_virt
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.endm
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.macro store, rd, rx:vararg
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ARM_BE8( rev \rd, \rd )
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str \rd, \rx
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.endm
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.macro load, rd, rx:vararg
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ldr \rd, \rx
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ARM_BE8( rev \rd, \rd )
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.endm
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.macro senduart,rd,rx
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store \rd, [\rx, #UART_TX << UART_SHIFT]
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.endm
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.macro busyuart,rd,rx
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1002: load \rd, [\rx, #UART_LSR << UART_SHIFT]
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and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
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teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
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bne 1002b
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.endm
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.macro waituarttxrdy,rd,rx
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.endm
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.macro waituartcts,rd,rx
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.endm
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/*
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* Storage for the state maintained by the macros above.
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*
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* In the kernel proper, this data is located in arch/arm/mach-bcm/brcmstb.c.
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* That's because this header is included from multiple files, and we only
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* want a single copy of the data. In particular, the UART probing code above
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* assumes it's running using physical addresses. This is true when this file
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* is included from head.o, but not when included from debug.o. So we need
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* to share the probe results between the two copies, rather than having
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* to re-run the probing again later.
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*
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* In the decompressor, we put the symbol/storage right here, since common.c
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* isn't included in the decompressor build. This symbol gets put in .text
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* even though it's really data, since .data is discarded from the
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* decompressor. Luckily, .text is writeable in the decompressor, unless
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* CONFIG_ZBOOT_ROM. That dependency is handled in arch/arm/Kconfig.debug.
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*/
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#if defined(ZIMAGE)
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brcmstb_uart_config:
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/* Debug UART initialization required */
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.word 1
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/* Debug UART physical address */
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.word 0
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/* Debug UART virtual address */
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.word 0
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#endif
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