d735599a06
Include capability flag PERF_PMU_CAP_EXTENDED_REGS for power10 and expose MMCR3, SIER2, SIER3 registers as part of extended regs. Also introduce PERF_REG_PMU_MASK_31 to define extended mask value at runtime for power10. Suggested-by: Ryan Grimm <grimm@linux.ibm.com> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Tested-by: Nageswara R Sastry <nasastry@in.ibm.com> Reviewed-by: Kajol Jain <kjain@linux.ibm.com> Reviewed-and-tested-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1596794701-23530-3-git-send-email-atrajeev@linux.vnet.ibm.com
71 lines
2 KiB
C
71 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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#ifndef _UAPI_ASM_POWERPC_PERF_REGS_H
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#define _UAPI_ASM_POWERPC_PERF_REGS_H
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enum perf_event_powerpc_regs {
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PERF_REG_POWERPC_R0,
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PERF_REG_POWERPC_R1,
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PERF_REG_POWERPC_R2,
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PERF_REG_POWERPC_R3,
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PERF_REG_POWERPC_R4,
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PERF_REG_POWERPC_R5,
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PERF_REG_POWERPC_R6,
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PERF_REG_POWERPC_R7,
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PERF_REG_POWERPC_R8,
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PERF_REG_POWERPC_R9,
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PERF_REG_POWERPC_R10,
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PERF_REG_POWERPC_R11,
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PERF_REG_POWERPC_R12,
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PERF_REG_POWERPC_R13,
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PERF_REG_POWERPC_R14,
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PERF_REG_POWERPC_R15,
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PERF_REG_POWERPC_R16,
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PERF_REG_POWERPC_R17,
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PERF_REG_POWERPC_R18,
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PERF_REG_POWERPC_R19,
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PERF_REG_POWERPC_R20,
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PERF_REG_POWERPC_R21,
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PERF_REG_POWERPC_R22,
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PERF_REG_POWERPC_R23,
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PERF_REG_POWERPC_R24,
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PERF_REG_POWERPC_R25,
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PERF_REG_POWERPC_R26,
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PERF_REG_POWERPC_R27,
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PERF_REG_POWERPC_R28,
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PERF_REG_POWERPC_R29,
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PERF_REG_POWERPC_R30,
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PERF_REG_POWERPC_R31,
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PERF_REG_POWERPC_NIP,
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PERF_REG_POWERPC_MSR,
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PERF_REG_POWERPC_ORIG_R3,
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PERF_REG_POWERPC_CTR,
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PERF_REG_POWERPC_LINK,
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PERF_REG_POWERPC_XER,
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PERF_REG_POWERPC_CCR,
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PERF_REG_POWERPC_SOFTE,
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PERF_REG_POWERPC_TRAP,
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PERF_REG_POWERPC_DAR,
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PERF_REG_POWERPC_DSISR,
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PERF_REG_POWERPC_SIER,
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PERF_REG_POWERPC_MMCRA,
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/* Extended registers */
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PERF_REG_POWERPC_MMCR0,
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PERF_REG_POWERPC_MMCR1,
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PERF_REG_POWERPC_MMCR2,
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PERF_REG_POWERPC_MMCR3,
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PERF_REG_POWERPC_SIER2,
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PERF_REG_POWERPC_SIER3,
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/* Max regs without the extended regs */
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PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1,
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};
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#define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1)
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/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 */
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#define PERF_REG_PMU_MASK_300 (((1ULL << (PERF_REG_POWERPC_MMCR2 + 1)) - 1) - PERF_REG_PMU_MASK)
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/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 */
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#define PERF_REG_PMU_MASK_31 (((1ULL << (PERF_REG_POWERPC_SIER3 + 1)) - 1) - PERF_REG_PMU_MASK)
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#define PERF_REG_MAX_ISA_300 (PERF_REG_POWERPC_MMCR2 + 1)
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#define PERF_REG_MAX_ISA_31 (PERF_REG_POWERPC_SIER3 + 1)
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#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */
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