a5b59a3f41
This patch adds support for the Variscite MX6 SoM Carrier Board. This Carrier-Board has the following : - LVDS interface for the VLCD-CAP-GLD-LVDS 7" LCD 800 x 480 touch display - HDMI Connector - USB Host + USB OTG Connector - 10/100/1000 Mbps Ethernet - miniPCI-Express slot - SD Card connector - Audio Headphone/Line In jack connectors - S-ATA - On-board DMIC - RS485 Header - CAN bus header - SPI header - Camera Interfaces header - OnBoard RTC with Coin Backup battery socket - RS232 Debug Header (IDC10) - RS232 DTE Product Page : https://www.variscite.com/product/single-board-computers/var-mx6customboard The dts file based on the ones provided by Variscite on their own kernel, but adapted for mainline. Cc: Pierluigi Passaro <pierluigi.p@variscite.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
247 lines
6 KiB
Text
247 lines
6 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Support for Variscite MX6 Carrier-board
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*
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* Copyright 2016 Variscite, Ltd. All Rights Reserved
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* Copyright 2022 Bootlin
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*/
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/dts-v1/;
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#include "imx6qdl-var-som.dtsi"
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#include <dt-bindings/pwm/pwm.h>
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/ {
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model = "Variscite i.MX6 QUAD/DUAL VAR-SOM-MX6 Custom Board";
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compatible = "variscite,mx6customboard", "variscite,var-som-imx6q", "fsl,imx6q";
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panel0: lvds-panel0 {
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compatible = "panel-lvds";
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backlight = <&backlight_lvds>;
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width-mm = <152>;
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height-mm = <91>;
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label = "etm070001adh6";
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data-mapping = "jeida-18";
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panel-timing {
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clock-frequency = <32000000>;
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hactive = <800>;
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vactive = <480>;
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hback-porch = <39>;
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hfront-porch = <39>;
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vback-porch = <29>;
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vfront-porch = <13>;
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hsync-len = <47>;
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vsync-len = <2>;
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};
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port {
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panel_in_lvds0: endpoint {
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remote-endpoint = <&lvds0_out>;
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};
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};
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};
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panel1: lvds-panel1 {
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compatible = "panel-lvds";
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width-mm = <152>;
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height-mm = <91>;
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data-mapping = "jeida-18";
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panel-timing {
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clock-frequency = <38251000>;
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hactive = <800>;
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vactive = <600>;
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hback-porch = <112>;
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hfront-porch = <32>;
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vback-porch = <3>;
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vfront-porch = <17>;
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hsync-len = <80>;
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vsync-len = <4>;
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};
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port {
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panel_in_lvds1: endpoint {
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remote-endpoint = <&lvds1_out>;
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};
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};
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};
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backlight_lvds: backlight-lvds {
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compatible = "pwm-backlight";
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pwms = <&pwm2 0 50000 0>;
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brightness-levels = <0 4 8 16 32 64 128 248>;
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default-brightness-level = <7>;
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power-supply = <®_3p3v>;
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};
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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touchscreen@24 {
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compatible = "cypress,tt21000";
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reg = <0x24>;
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interrupt-parent = <&gpio3>;
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interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
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reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
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vdd-supply = <®_3p3v>;
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touchscreen-size-x = <880>;
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touchscreen-size-y = <1280>;
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};
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touchscreen@38 {
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compatible = "edt,edt-ft5306";
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reg = <0x38>;
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interrupt-parent = <&gpio3>;
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interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
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touchscreen-size-x = <1800>;
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touchscreen-size-y = <1000>;
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};
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};
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&iomuxc {
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pinctrl_camera: cameragrp {
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fsl,pins = <
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MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
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MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
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MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
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MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
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MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
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MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
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MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
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MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
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MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0
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MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
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MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
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MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
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MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
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>;
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};
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pinctrl_ipu1: ipu1grp {
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fsl,pins = <
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MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
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MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
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MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
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MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
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MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10
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MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
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MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
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MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
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MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
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MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
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MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
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MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
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MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
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MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
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MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
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MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
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MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
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MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
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MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
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MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
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MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
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MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
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MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
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MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
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MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
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MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
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MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
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MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
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MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
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MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
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MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
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MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
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>;
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};
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pinctrl_usbotg_var: usbotggrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x17059
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
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MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
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MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
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MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
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MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
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MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
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MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
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MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
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MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
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MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
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MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
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>;
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};
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};
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&ldb {
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status = "okay";
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lvds-channel@0 {
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fsl,data-mapping = "spwg";
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fsl,data-width = <24>;
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status = "okay";
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port@4 {
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reg = <4>;
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lvds0_out: endpoint {
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remote-endpoint = <&panel_in_lvds0>;
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};
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};
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};
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lvds-channel@1 {
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fsl,data-mapping = "spwg";
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fsl,data-width = <24>;
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status = "okay";
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port@4 {
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reg = <4>;
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lvds1_out: endpoint {
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remote-endpoint = <&panel_in_lvds1>;
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};
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};
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};
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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uart-has-rtscts;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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