984b265ff6
Similar to GFX11, GFX12 supports trapping on wave start and end. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
377 lines
11 KiB
C
377 lines
11 KiB
C
/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "amdgpu.h"
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#include "amdgpu_amdkfd.h"
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#include "gc/gc_12_0_0_offset.h"
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#include "gc/gc_12_0_0_sh_mask.h"
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#include "soc24.h"
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#include <uapi/linux/kfd_ioctl.h>
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static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,
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uint32_t queue, uint32_t vmid)
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{
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mutex_lock(&adev->srbm_mutex);
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soc24_grbm_select(adev, mec, pipe, queue, vmid);
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}
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static void unlock_srbm(struct amdgpu_device *adev)
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{
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soc24_grbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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}
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static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,
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uint32_t queue_id)
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{
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uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
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uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
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lock_srbm(adev, mec, pipe, queue_id, 0);
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}
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static void release_queue(struct amdgpu_device *adev)
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{
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unlock_srbm(adev);
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}
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static int init_interrupts_v12(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t inst)
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{
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uint32_t mec;
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uint32_t pipe;
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mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
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pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
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lock_srbm(adev, mec, pipe, 0, 0);
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WREG32_SOC15(GC, 0, regCPC_INT_CNTL,
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CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
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CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
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unlock_srbm(adev);
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return 0;
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}
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static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
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unsigned int engine_id,
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unsigned int queue_id)
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{
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uint32_t sdma_engine_reg_base = 0;
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uint32_t sdma_rlc_reg_offset;
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switch (engine_id) {
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case 0:
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
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regSDMA0_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL;
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break;
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case 1:
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
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regSDMA1_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL;
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break;
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default:
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BUG();
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}
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sdma_rlc_reg_offset = sdma_engine_reg_base
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+ queue_id * (regSDMA0_QUEUE1_RB_CNTL - regSDMA0_QUEUE0_RB_CNTL);
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pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
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queue_id, sdma_rlc_reg_offset);
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return sdma_rlc_reg_offset;
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}
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static int hqd_dump_v12(struct amdgpu_device *adev,
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uint32_t pipe_id, uint32_t queue_id,
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uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)
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{
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uint32_t i = 0, reg;
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#define HQD_N_REGS 56
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#define DUMP_REG(addr) do { \
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if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
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break; \
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(*dump)[i][0] = (addr) << 2; \
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(*dump)[i++][1] = RREG32(addr); \
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} while (0)
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*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
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if (*dump == NULL)
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return -ENOMEM;
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acquire_queue(adev, pipe_id, queue_id);
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for (reg = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR);
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reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++)
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DUMP_REG(reg);
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release_queue(adev);
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WARN_ON_ONCE(i != HQD_N_REGS);
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*n_regs = i;
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return 0;
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}
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static int hqd_sdma_dump_v12(struct amdgpu_device *adev,
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uint32_t engine_id, uint32_t queue_id,
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uint32_t (**dump)[2], uint32_t *n_regs)
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{
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uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
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engine_id, queue_id);
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uint32_t i = 0, reg;
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const uint32_t first_reg = regSDMA0_QUEUE0_RB_CNTL;
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const uint32_t last_reg = regSDMA0_QUEUE0_CONTEXT_STATUS;
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#undef HQD_N_REGS
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#define HQD_N_REGS (last_reg - first_reg + 1)
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*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
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if (*dump == NULL)
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return -ENOMEM;
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for (reg = first_reg;
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reg <= last_reg; reg++)
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DUMP_REG(sdma_rlc_reg_offset + reg);
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WARN_ON_ONCE(i != HQD_N_REGS);
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*n_regs = i;
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return 0;
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}
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static int wave_control_execute_v12(struct amdgpu_device *adev,
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uint32_t gfx_index_val,
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uint32_t sq_cmd, uint32_t inst)
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{
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uint32_t data = 0;
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mutex_lock(&adev->grbm_idx_mutex);
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WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val);
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WREG32(SOC15_REG_OFFSET(GC, 0, regSQ_CMD), sq_cmd);
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data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
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INSTANCE_BROADCAST_WRITES, 1);
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data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
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SA_BROADCAST_WRITES, 1);
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data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
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SE_BROADCAST_WRITES, 1);
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WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data);
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mutex_unlock(&adev->grbm_idx_mutex);
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return 0;
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}
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/* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */
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static uint32_t kgd_gfx_v12_enable_debug_trap(struct amdgpu_device *adev,
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bool restore_dbg_registers,
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uint32_t vmid)
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{
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uint32_t data = 0;
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);
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return data;
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}
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/* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */
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static uint32_t kgd_gfx_v12_disable_debug_trap(struct amdgpu_device *adev,
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bool keep_trap_enabled,
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uint32_t vmid)
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{
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uint32_t data = 0;
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);
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return data;
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}
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static int kgd_gfx_v12_validate_trap_override_request(struct amdgpu_device *adev,
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uint32_t trap_override,
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uint32_t *trap_mask_supported)
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{
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*trap_mask_supported &= KFD_DBG_TRAP_MASK_FP_INVALID |
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KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL |
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KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO |
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KFD_DBG_TRAP_MASK_FP_OVERFLOW |
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KFD_DBG_TRAP_MASK_FP_UNDERFLOW |
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KFD_DBG_TRAP_MASK_FP_INEXACT |
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KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO |
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KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH |
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KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION |
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KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START |
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KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END;
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if (trap_override != KFD_DBG_TRAP_OVERRIDE_OR &&
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trap_override != KFD_DBG_TRAP_OVERRIDE_REPLACE)
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return -EPERM;
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return 0;
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}
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static uint32_t trap_mask_map_sw_to_hw(uint32_t mask)
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{
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uint32_t trap_on_start = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START) ? 1 : 0;
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uint32_t trap_on_end = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END) ? 1 : 0;
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uint32_t excp_en = mask & (KFD_DBG_TRAP_MASK_FP_INVALID |
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KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL |
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KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO |
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KFD_DBG_TRAP_MASK_FP_OVERFLOW |
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KFD_DBG_TRAP_MASK_FP_UNDERFLOW |
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KFD_DBG_TRAP_MASK_FP_INEXACT |
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KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO |
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KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH |
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KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION);
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uint32_t ret;
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ret = REG_SET_FIELD(0, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, excp_en);
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ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START, trap_on_start);
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ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END, trap_on_end);
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return ret;
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}
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static uint32_t trap_mask_map_hw_to_sw(uint32_t mask)
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{
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uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);
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if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START))
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ret |= KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START;
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if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END))
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ret |= KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END;
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return ret;
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}
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/* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */
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static uint32_t kgd_gfx_v12_set_wave_launch_trap_override(struct amdgpu_device *adev,
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uint32_t vmid,
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uint32_t trap_override,
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uint32_t trap_mask_bits,
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uint32_t trap_mask_request,
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uint32_t *trap_mask_prev,
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uint32_t kfd_dbg_trap_cntl_prev)
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{
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uint32_t data = 0;
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*trap_mask_prev = trap_mask_map_hw_to_sw(kfd_dbg_trap_cntl_prev);
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data = (trap_mask_bits & trap_mask_request) | (*trap_mask_prev & ~trap_mask_request);
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data = trap_mask_map_sw_to_hw(data);
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override);
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return data;
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}
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/* returns STALL_VMID or LAUNCH_MODE. */
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static uint32_t kgd_gfx_v12_set_wave_launch_mode(struct amdgpu_device *adev,
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uint8_t wave_launch_mode,
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uint32_t vmid)
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{
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uint32_t data = 0;
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bool is_stall_mode = wave_launch_mode == 4;
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if (is_stall_mode)
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, STALL_VMID,
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1);
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else
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, LAUNCH_MODE,
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wave_launch_mode);
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return data;
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}
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#define TCP_WATCH_STRIDE (regTCP_WATCH1_ADDR_H - regTCP_WATCH0_ADDR_H)
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static uint32_t kgd_gfx_v12_set_address_watch(struct amdgpu_device *adev,
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uint64_t watch_address,
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uint32_t watch_address_mask,
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uint32_t watch_id,
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uint32_t watch_mode,
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uint32_t debug_vmid,
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uint32_t inst)
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{
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uint32_t watch_address_high;
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uint32_t watch_address_low;
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uint32_t watch_address_cntl;
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watch_address_cntl = 0;
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watch_address_low = lower_32_bits(watch_address);
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watch_address_high = upper_32_bits(watch_address) & 0xffff;
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watch_address_cntl = REG_SET_FIELD(watch_address_cntl,
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TCP_WATCH0_CNTL,
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MODE,
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watch_mode);
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watch_address_cntl = REG_SET_FIELD(watch_address_cntl,
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TCP_WATCH0_CNTL,
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MASK,
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watch_address_mask >> 7);
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watch_address_cntl = REG_SET_FIELD(watch_address_cntl,
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TCP_WATCH0_CNTL,
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VALID,
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1);
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WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) +
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(watch_id * TCP_WATCH_STRIDE)),
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watch_address_high);
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WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) +
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(watch_id * TCP_WATCH_STRIDE)),
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watch_address_low);
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return watch_address_cntl;
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}
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static uint32_t kgd_gfx_v12_clear_address_watch(struct amdgpu_device *adev,
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uint32_t watch_id)
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{
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return 0;
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}
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const struct kfd2kgd_calls gfx_v12_kfd2kgd = {
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.init_interrupts = init_interrupts_v12,
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.hqd_dump = hqd_dump_v12,
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.hqd_sdma_dump = hqd_sdma_dump_v12,
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.wave_control_execute = wave_control_execute_v12,
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.get_atc_vmid_pasid_mapping_info = NULL,
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.enable_debug_trap = kgd_gfx_v12_enable_debug_trap,
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.disable_debug_trap = kgd_gfx_v12_disable_debug_trap,
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.validate_trap_override_request = kgd_gfx_v12_validate_trap_override_request,
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.set_wave_launch_trap_override = kgd_gfx_v12_set_wave_launch_trap_override,
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.set_wave_launch_mode = kgd_gfx_v12_set_wave_launch_mode,
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.set_address_watch = kgd_gfx_v12_set_address_watch,
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.clear_address_watch = kgd_gfx_v12_clear_address_watch,
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};
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