126be9b2be
This patch tries to solve the basic problem we also need to sync to the KFD fences of the BO because otherwise it can be that we clear PTEs while the KFD queues are still running. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
65 lines
2.4 KiB
C
65 lines
2.4 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König
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*/
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#ifndef __AMDGPU_SYNC_H__
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#define __AMDGPU_SYNC_H__
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#include <linux/hashtable.h>
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struct dma_fence;
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struct dma_resv;
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struct amdgpu_device;
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struct amdgpu_ring;
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struct amdgpu_job;
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enum amdgpu_sync_mode {
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AMDGPU_SYNC_ALWAYS,
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AMDGPU_SYNC_NE_OWNER,
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AMDGPU_SYNC_EQ_OWNER,
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AMDGPU_SYNC_EXPLICIT
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};
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/*
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* Container for fences used to sync command submissions.
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*/
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struct amdgpu_sync {
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DECLARE_HASHTABLE(fences, 4);
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};
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void amdgpu_sync_create(struct amdgpu_sync *sync);
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int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f);
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int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync,
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struct dma_resv *resv, enum amdgpu_sync_mode mode,
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void *owner);
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int amdgpu_sync_kfd(struct amdgpu_sync *sync, struct dma_resv *resv);
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struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
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struct amdgpu_ring *ring);
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struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
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int amdgpu_sync_clone(struct amdgpu_sync *source, struct amdgpu_sync *clone);
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int amdgpu_sync_push_to_job(struct amdgpu_sync *sync, struct amdgpu_job *job);
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int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr);
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void amdgpu_sync_free(struct amdgpu_sync *sync);
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int amdgpu_sync_init(void);
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void amdgpu_sync_fini(void);
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#endif
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