748bd8ebae
Access ltr through pci cfg space instead of mmio while programing aspm on gfx12 Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
520 lines
19 KiB
C
520 lines
19 KiB
C
/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_atombios.h"
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#include "nbif_v6_3_1.h"
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#include "nbif/nbif_6_3_1_offset.h"
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#include "nbif/nbif_6_3_1_sh_mask.h"
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#include "pcie/pcie_6_1_0_offset.h"
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#include "pcie/pcie_6_1_0_sh_mask.h"
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#include <uapi/linux/kfd_ioctl.h>
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static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev)
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{
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WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
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adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
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WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
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adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
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}
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static u32 nbif_v6_3_1_get_rev_id(struct amdgpu_device *adev)
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{
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u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
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tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
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tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
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return tmp;
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}
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static void nbif_v6_3_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
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{
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if (enable)
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WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
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BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
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BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
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else
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WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
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}
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static u32 nbif_v6_3_1_get_memsize(struct amdgpu_device *adev)
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{
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return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
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}
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static void nbif_v6_3_1_sdma_doorbell_range(struct amdgpu_device *adev,
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int instance, bool use_doorbell,
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int doorbell_index,
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int doorbell_size)
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{
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if (instance == 0) {
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u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL);
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if (use_doorbell) {
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
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S2A_DOORBELL_PORT2_ENABLE,
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0x1);
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
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S2A_DOORBELL_PORT2_AWID,
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0xe);
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
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S2A_DOORBELL_PORT2_RANGE_OFFSET,
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doorbell_index);
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
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S2A_DOORBELL_PORT2_RANGE_SIZE,
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doorbell_size);
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
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S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE,
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0x3);
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} else
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
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S2A_DOORBELL_PORT2_RANGE_SIZE,
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0);
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WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range);
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}
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}
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static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev,
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bool use_doorbell, int doorbell_index,
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int instance)
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{
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u32 doorbell_range;
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if (instance)
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doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL);
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else
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doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL);
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if (use_doorbell) {
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
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S2A_DOORBELL_PORT4_ENABLE,
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0x1);
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
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S2A_DOORBELL_PORT4_AWID,
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instance ? 0x7 : 0x4);
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
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S2A_DOORBELL_PORT4_RANGE_OFFSET,
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doorbell_index);
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
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S2A_DOORBELL_PORT4_RANGE_SIZE,
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8);
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
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S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE,
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instance ? 0x7 : 0x4);
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} else
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
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S2A_DOORBELL_PORT4_RANGE_SIZE,
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0);
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if (instance)
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WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
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else
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WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range);
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}
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static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev)
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{
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WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);
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WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d);
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}
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static void nbif_v6_3_1_enable_doorbell_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN,
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BIF_DOORBELL_APER_EN, enable ? 1 : 0);
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}
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static void
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nbif_v6_3_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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u32 tmp = 0;
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if (enable) {
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tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_EN, 1) |
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REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_MODE, 1) |
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REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_SIZE, 0);
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WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
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lower_32_bits(adev->doorbell.base));
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WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
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upper_32_bits(adev->doorbell.base));
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}
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WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
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}
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static void nbif_v6_3_1_ih_doorbell_range(struct amdgpu_device *adev,
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bool use_doorbell, int doorbell_index)
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{
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u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL);
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if (use_doorbell) {
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_ENABLE,
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0x1);
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_AWID,
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0x0);
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_RANGE_OFFSET,
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doorbell_index);
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_RANGE_SIZE,
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2);
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
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0x0);
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} else
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_RANGE_SIZE,
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0);
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WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range);
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}
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static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev)
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{
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u32 interrupt_cntl;
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/* setup interrupt control */
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WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
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interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
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/*
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* BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
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* BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
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*/
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interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
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IH_DUMMY_RD_OVERRIDE, 0);
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/* BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
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interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
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IH_REQ_NONSNOOP_EN, 0);
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WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
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}
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static void
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nbif_v6_3_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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}
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static void
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nbif_v6_3_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
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bool enable)
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{
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}
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static void
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nbif_v6_3_1_get_clockgating_state(struct amdgpu_device *adev,
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u64 *flags)
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{
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}
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static u32 nbif_v6_3_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
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}
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static u32 nbif_v6_3_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
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}
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static u32 nbif_v6_3_1_get_pcie_index_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
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}
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static u32 nbif_v6_3_1_get_pcie_data_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
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}
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const struct nbio_hdp_flush_reg nbif_v6_3_1_hdp_flush_reg = {
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.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
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.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
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.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
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.ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
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.ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
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.ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
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.ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
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.ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
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.ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
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.ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
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.ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
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.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
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};
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static void nbif_v6_3_1_init_registers(struct amdgpu_device *adev)
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{
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uint32_t data;
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data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2);
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data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK;
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WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data);
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}
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static u32 nbif_v6_3_1_get_rom_offset(struct amdgpu_device *adev)
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{
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u32 data, rom_offset;
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data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL);
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rom_offset = REG_GET_FIELD(data, REGS_ROM_OFFSET_CTRL, ROM_OFFSET);
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return rom_offset;
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}
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#ifdef CONFIG_PCIEASPM
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static void nbif_v6_3_1_program_ltr(struct amdgpu_device *adev)
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{
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uint32_t def, data;
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u16 devctl2;
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def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
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data = 0x35EB;
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data &= ~RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;
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data &= ~RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK;
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if (def != data)
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WREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);
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def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2);
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data &= ~RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;
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if (def != data)
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WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data);
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pcie_capability_read_word(adev->pdev, PCI_EXP_DEVCTL2, &devctl2);
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if (adev->pdev->ltr_path == (devctl2 & PCI_EXP_DEVCTL2_LTR_EN))
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return;
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if (adev->pdev->ltr_path)
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pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN);
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else
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pcie_capability_clear_word(adev->pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN);
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}
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#endif
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static void nbif_v6_3_1_program_aspm(struct amdgpu_device *adev)
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{
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#ifdef CONFIG_PCIEASPM
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uint32_t def, data;
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u16 devctl2, ltr;
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def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL);
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data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
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data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
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data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
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if (def != data)
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WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data);
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def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7);
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data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;
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if (def != data)
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WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7, data);
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def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3);
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|
data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
|
|
if (def != data)
|
|
WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3, data);
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|
|
|
def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);
|
|
data &= ~RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;
|
|
data &= ~RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;
|
|
if (def != data)
|
|
WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data);
|
|
|
|
def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);
|
|
data &= ~RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;
|
|
if (def != data)
|
|
WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data);
|
|
|
|
pcie_capability_read_word(adev->pdev, PCI_EXP_DEVCTL2, &devctl2);
|
|
data = def = devctl2;
|
|
data &= ~PCI_EXP_DEVCTL2_LTR_EN;
|
|
if (def != data)
|
|
pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2, (u16)data);
|
|
|
|
ltr = pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_LTR);
|
|
|
|
if (ltr) {
|
|
pci_write_config_dword(adev->pdev, ltr + PCI_LTR_MAX_SNOOP_LAT, 0x10011001);
|
|
}
|
|
|
|
#if 0
|
|
/* regPSWUSP0_PCIE_LC_CNTL2 should be replace by PCIE_LC_CNTL2 or someone else ? */
|
|
def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2);
|
|
data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
|
|
PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
|
|
data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;
|
|
if (def != data)
|
|
WREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2, data);
|
|
#endif
|
|
def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4);
|
|
data |= PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK;
|
|
if (def != data)
|
|
WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4, data);
|
|
|
|
def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL);
|
|
data |= PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK;
|
|
if (def != data)
|
|
WREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL, data);
|
|
|
|
nbif_v6_3_1_program_ltr(adev);
|
|
|
|
def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);
|
|
data |= 0x5DE0 << RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
|
|
data |= 0x0010 << RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;
|
|
if (def != data)
|
|
WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data);
|
|
|
|
def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);
|
|
data |= 0x0010 << RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;
|
|
if (def != data)
|
|
WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data);
|
|
|
|
def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL);
|
|
data |= 0x0 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
|
|
data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
|
|
data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
|
|
if (def != data)
|
|
WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data);
|
|
|
|
def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3);
|
|
data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
|
|
if (def != data)
|
|
WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3, data);
|
|
#endif
|
|
}
|
|
|
|
#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
|
|
|
|
static void nbif_v6_3_1_set_reg_remap(struct amdgpu_device *adev)
|
|
{
|
|
if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
|
|
adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
|
|
adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
|
|
} else {
|
|
adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
|
|
regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
|
|
adev->rmmio_remap.bus_addr = 0;
|
|
}
|
|
}
|
|
|
|
const struct amdgpu_nbio_funcs nbif_v6_3_1_funcs = {
|
|
.get_hdp_flush_req_offset = nbif_v6_3_1_get_hdp_flush_req_offset,
|
|
.get_hdp_flush_done_offset = nbif_v6_3_1_get_hdp_flush_done_offset,
|
|
.get_pcie_index_offset = nbif_v6_3_1_get_pcie_index_offset,
|
|
.get_pcie_data_offset = nbif_v6_3_1_get_pcie_data_offset,
|
|
.get_rev_id = nbif_v6_3_1_get_rev_id,
|
|
.mc_access_enable = nbif_v6_3_1_mc_access_enable,
|
|
.get_memsize = nbif_v6_3_1_get_memsize,
|
|
.sdma_doorbell_range = nbif_v6_3_1_sdma_doorbell_range,
|
|
.vcn_doorbell_range = nbif_v6_3_1_vcn_doorbell_range,
|
|
.gc_doorbell_init = nbif_v6_3_1_gc_doorbell_init,
|
|
.enable_doorbell_aperture = nbif_v6_3_1_enable_doorbell_aperture,
|
|
.enable_doorbell_selfring_aperture = nbif_v6_3_1_enable_doorbell_selfring_aperture,
|
|
.ih_doorbell_range = nbif_v6_3_1_ih_doorbell_range,
|
|
.update_medium_grain_clock_gating = nbif_v6_3_1_update_medium_grain_clock_gating,
|
|
.update_medium_grain_light_sleep = nbif_v6_3_1_update_medium_grain_light_sleep,
|
|
.get_clockgating_state = nbif_v6_3_1_get_clockgating_state,
|
|
.ih_control = nbif_v6_3_1_ih_control,
|
|
.init_registers = nbif_v6_3_1_init_registers,
|
|
.remap_hdp_registers = nbif_v6_3_1_remap_hdp_registers,
|
|
.get_rom_offset = nbif_v6_3_1_get_rom_offset,
|
|
.program_aspm = nbif_v6_3_1_program_aspm,
|
|
.set_reg_remap = nbif_v6_3_1_set_reg_remap,
|
|
};
|
|
|
|
|
|
static void nbif_v6_3_1_sriov_ih_doorbell_range(struct amdgpu_device *adev,
|
|
bool use_doorbell, int doorbell_index)
|
|
{
|
|
}
|
|
|
|
static void nbif_v6_3_1_sriov_sdma_doorbell_range(struct amdgpu_device *adev,
|
|
int instance, bool use_doorbell,
|
|
int doorbell_index,
|
|
int doorbell_size)
|
|
{
|
|
}
|
|
|
|
static void nbif_v6_3_1_sriov_vcn_doorbell_range(struct amdgpu_device *adev,
|
|
bool use_doorbell,
|
|
int doorbell_index, int instance)
|
|
{
|
|
}
|
|
|
|
static void nbif_v6_3_1_sriov_gc_doorbell_init(struct amdgpu_device *adev)
|
|
{
|
|
}
|
|
|
|
const struct amdgpu_nbio_funcs nbif_v6_3_1_sriov_funcs = {
|
|
.get_hdp_flush_req_offset = nbif_v6_3_1_get_hdp_flush_req_offset,
|
|
.get_hdp_flush_done_offset = nbif_v6_3_1_get_hdp_flush_done_offset,
|
|
.get_pcie_index_offset = nbif_v6_3_1_get_pcie_index_offset,
|
|
.get_pcie_data_offset = nbif_v6_3_1_get_pcie_data_offset,
|
|
.get_rev_id = nbif_v6_3_1_get_rev_id,
|
|
.mc_access_enable = nbif_v6_3_1_mc_access_enable,
|
|
.get_memsize = nbif_v6_3_1_get_memsize,
|
|
.sdma_doorbell_range = nbif_v6_3_1_sriov_sdma_doorbell_range,
|
|
.vcn_doorbell_range = nbif_v6_3_1_sriov_vcn_doorbell_range,
|
|
.gc_doorbell_init = nbif_v6_3_1_sriov_gc_doorbell_init,
|
|
.enable_doorbell_aperture = nbif_v6_3_1_enable_doorbell_aperture,
|
|
.enable_doorbell_selfring_aperture = nbif_v6_3_1_enable_doorbell_selfring_aperture,
|
|
.ih_doorbell_range = nbif_v6_3_1_sriov_ih_doorbell_range,
|
|
.update_medium_grain_clock_gating = nbif_v6_3_1_update_medium_grain_clock_gating,
|
|
.update_medium_grain_light_sleep = nbif_v6_3_1_update_medium_grain_light_sleep,
|
|
.get_clockgating_state = nbif_v6_3_1_get_clockgating_state,
|
|
.ih_control = nbif_v6_3_1_ih_control,
|
|
.init_registers = nbif_v6_3_1_init_registers,
|
|
.remap_hdp_registers = nbif_v6_3_1_remap_hdp_registers,
|
|
.get_rom_offset = nbif_v6_3_1_get_rom_offset,
|
|
.set_reg_remap = nbif_v6_3_1_set_reg_remap,
|
|
};
|