Guchun Chen 7551f70ab9 drm/amdgpu: fix the missed handling for SDMA2 and SDMA3 ... There is no base reg offset or ip_version set for SDMA2 and SDMA3 on SIENNA_CICHLID, so add them. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Kevin Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-12-01 17:00:55 -05:00
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drm	drm/amdgpu: fix the missed handling for SDMA2 and SDMA3	2021-12-01 17:00:55 -05:00
host1x	gpu: host1x: Plug potential memory leak	2021-09-16 18:06:52 +02:00
ipu-v3	media: i.MX6: Support 16-bit BT.1120 video input	2021-10-19 08:08:38 +01:00
trace
vga	vgaarb: don't pass a cookie to vga_client_register	2021-07-21 10:29:10 +02:00
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