Changfeng f6f75ebdc0 drm/amd/pm: update smu10.h WORKLOAD_PPLIB setting for raven ... When using old WORKLOAD_PPLIB setting in smu10.h, there is problem that it can't be able to switch to mak gpu clk during compute workload. It needs to update WORKLOAD_PPLIB setting to fix this issue. Signed-off-by: Changfeng <Changfeng.Zhu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-12-08 23:06:15 -05:00
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vega12
amd_powerplay.h
amdgpu_dpm.h	drm/amd/powerplay: add one sysfs file to support the feature to modify gfx clock on Raven/Raven2/Picasso APU.	2020-09-29 16:12:16 -04:00
amdgpu_pm.h
amdgpu_smu.h	drm/amdgpu/swsmu: add metrics enums for voltage	2020-12-02 17:37:17 -05:00
arcturus_ppsmc.h
cz_ppsmc.h
fiji_ppsmc.h
hardwaremanager.h
hwmgr.h	drm/amd/pm/powerplay/hwmgr/hwmgr: Move 'vega20_hwmgr_init()'s prototype to shared header	2020-12-01 16:04:45 -05:00
polaris10_pwrvirus.h
power_state.h
pp_debug.h
pp_endian.h
pp_thermal.h	drm/amd/pm/inc/pp_thermal: Mark 'SMU7Thermal{WithDelay}Policy' as __maybe_unused	2020-12-01 16:04:44 -05:00
ppinterrupt.h
rv_ppsmc.h	drm/amdgpu: add amdgpu_gfx_state_change_set() set gfx power change entry (v2)	2020-11-13 17:29:45 -05:00
smu7.h
smu7_common.h
smu7_discrete.h
smu7_fusion.h
smu7_ppsmc.h	drm/amd/pm: correct Polaris DIDT configurations	2020-10-27 11:59:16 -04:00
smu8.h
smu8_fusion.h
smu9.h
smu9_driver_if.h
smu10.h	drm/amd/pm: update smu10.h WORKLOAD_PPLIB setting for raven	2020-12-08 23:06:15 -05:00
smu10_driver_if.h	drm/amd/pm: add Raven2 watermark WmType setting	2020-09-17 17:48:18 -04:00
smu11_driver_if.h
smu11_driver_if_arcturus.h
smu11_driver_if_navi10.h
smu11_driver_if_sienna_cichlid.h	drm/amd/pm: update driver if file for sienna cichlid	2020-11-16 12:18:10 -05:00
smu11_driver_if_vangogh.h	drm/amd/pm: update the swSMU headers for vangogh	2020-11-13 00:12:51 -05:00
smu12_driver_if.h
smu71.h
smu71_discrete.h
smu72.h
smu72_discrete.h
smu73.h
smu73_discrete.h
smu74.h
smu74_discrete.h	drm/amd/pm: correct VR shared rail info	2020-10-27 11:58:57 -04:00
smu75.h
smu75_discrete.h
smu_11_0_cdr_table.h	drm/amd/pm: implement a new umc cdr workaround	2020-09-17 17:46:40 -04:00
smu_types.h	drm/amd/pm: remove some redundant smu message mapping for vangogh	2020-10-30 00:58:26 -04:00
smu_ucode_xfer_cz.h
smu_ucode_xfer_vi.h
smu_v11_0.h	drm/amd/pm: update driver if version for dimgrey_cavefish	2020-12-08 23:05:21 -05:00
smu_v11_0_7_ppsmc.h
smu_v11_0_7_pptable.h
smu_v11_0_ppsmc.h	drm/amd/pm: apply the CDR workarounds only with some specific UMC firmwares(V2)	2020-09-17 17:46:47 -04:00
smu_v11_0_pptable.h
smu_v11_5_pmfw.h	drm/amd/pm: update the swSMU headers for vangogh	2020-11-13 00:12:51 -05:00
smu_v11_5_ppsmc.h	drm/amd/pm: update the swSMU headers for vangogh	2020-11-13 00:12:51 -05:00
smu_v12_0.h
smu_v12_0_ppsmc.h
smumgr.h	drm/amd/pm: perform SMC reset on suspend/hibernation	2020-10-30 01:00:43 -04:00
tonga_ppsmc.h
vega10_ppsmc.h
vega12_ppsmc.h
vega20_ppsmc.h