Charlie Jenkins 7c5d838d70 documentation: Fix riscv cmodx example ... ON/OFF in the keys was swapped between the first and second argument of the prctl. The prctl key is always PR_RISCV_SET_ICACHE_FLUSH_CTX, and the second argument can be PR_RISCV_CTX_SW_FENCEI_ON or PR_RISCV_CTX_SW_FENCEI_OFF. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Fixes: 6a08e4709c ("documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl") Link: https://lore.kernel.org/r/20240628-fix_cmodx_example-v1-1-e6c6523bc163@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2024-07-01 10:50:18 -07:00
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acpi.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
boot-image-header.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
boot.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
cmodx.rst	documentation: Fix riscv cmodx example	2024-07-01 10:50:18 -07:00
features.rst	docs: kernel_feat.py: fix potential command injection	2024-01-11 09:21:01 -07:00
hwprobe.rst	riscv: hwprobe: export Zihintpause ISA extension	2024-04-28 14:50:38 -07:00
index.rst	documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl	2024-04-18 08:10:59 -07:00
patch-acceptance.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
uabi.rst	Documentation: RISC-V: uabi: Only scalar misaligned loads are supported	2024-05-30 09:42:53 -07:00
vector.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
vm-layout.rst	docs: riscv: Define behavior of mmap	2024-03-14 08:46:15 -07:00