ffcdf47379
A properly clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
33 lines
841 B
C
33 lines
841 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2013 John Crispin <john@phrozen.org>
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*/
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#ifndef _RT288X_REGS_H_
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#define _RT288X_REGS_H_
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#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x)))
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#define RT2880_SYSC_BASE IOMEM(0x00300000)
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#define SYSC_REG_CHIP_NAME0 0x00
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#define SYSC_REG_CHIP_NAME1 0x04
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#define SYSC_REG_CHIP_ID 0x0c
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#define SYSC_REG_SYSTEM_CONFIG 0x10
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#define RT2880_CHIP_NAME0 0x38325452
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#define RT2880_CHIP_NAME1 0x20203038
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#define CHIP_ID_ID_MASK 0xff
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#define CHIP_ID_ID_SHIFT 8
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#define CHIP_ID_REV_MASK 0xff
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#define RT2880_SDRAM_BASE 0x08000000
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#define RT2880_MEM_SIZE_MIN 2
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#define RT2880_MEM_SIZE_MAX 128
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#endif
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