cd2e31a9ab
The same parade TCON issue can potentially happen on Phoenix, and the same PSR resilience changes have been ported into the DMUB firmware. Don't allow running PSR-SU unless on the newer firmware. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
67 lines
2.3 KiB
C
67 lines
2.3 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "../dmub_srv.h"
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#include "dmub_reg.h"
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#include "dmub_dcn314.h"
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#include "dcn/dcn_3_1_4_offset.h"
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#include "dcn/dcn_3_1_4_sh_mask.h"
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#define DCN_BASE__INST0_SEG0 0x00000012
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#define DCN_BASE__INST0_SEG1 0x000000C0
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#define DCN_BASE__INST0_SEG2 0x000034C0
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#define DCN_BASE__INST0_SEG3 0x00009000
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#define DCN_BASE__INST0_SEG4 0x02403C00
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#define DCN_BASE__INST0_SEG5 0
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#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
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#define CTX dmub
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#define REGS dmub->regs_dcn31
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#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
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/* Registers. */
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const struct dmub_srv_dcn31_regs dmub_srv_dcn314_regs = {
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#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
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{
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DMUB_DCN31_REGS()
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DMCUB_INTERNAL_REGS()
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},
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#undef DMUB_SR
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#define DMUB_SF(reg, field) FD_MASK(reg, field),
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{ DMUB_DCN31_FIELDS() },
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#undef DMUB_SF
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#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
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{ DMUB_DCN31_FIELDS() },
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#undef DMUB_SF
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};
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bool dmub_dcn314_is_psrsu_supported(struct dmub_srv *dmub)
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{
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return dmub->fw_version >= DMUB_FW_VERSION(8, 0, 16);
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}
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