bdf79b1286
Some of the newer silicon versions in CN10K series supports a feature where in the current PTP timestamp in HW can be updated atomically without losing any cpu cycles unlike read/modify/write register. This patch uses this feature so that PTP accuracy can be improved while adjusting the master offset in HW. There is no need for SW timecounter when using this feature. So removed references to SW timecounter wherever appropriate. Signed-off-by: Sai Krishna <saikrishnag@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com> Reviewed-by: Simon Horman <horms@kernel.org> Reviewed-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
33 lines
624 B
C
33 lines
624 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Marvell PTP driver
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*
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* Copyright (C) 2020 Marvell.
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*
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*/
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#ifndef PTP_H
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#define PTP_H
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#include <linux/timecounter.h>
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#include <linux/time64.h>
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#include <linux/spinlock.h>
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struct ptp {
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struct pci_dev *pdev;
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void __iomem *reg_base;
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u64 (*read_ptp_tstmp)(struct ptp *ptp);
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spinlock_t ptp_lock; /* lock */
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struct hrtimer hrtimer;
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ktime_t last_ts;
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u32 clock_rate;
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u32 clock_period;
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};
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struct rvu;
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struct ptp *ptp_get(void);
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void ptp_put(struct ptp *ptp);
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void ptp_start(struct rvu *rvu, u64 sclk, u32 ext_clk_freq, u32 extts);
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extern struct pci_driver ptp_driver;
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#endif
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