b79f300c1f
Introduce support for nonstandard noncoherent systems in the RISC-V architecture. It enables function pointer support to handle cache management in such systems. This patch adds a new configuration option called "RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer support for cache management in nonstandard noncoherent systems. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1 Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> # Link: https://lore.kernel.org/r/20230818135723.80612-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
34 lines
836 B
C
34 lines
836 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 Ventana Micro Systems Inc.
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*/
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#include <linux/export.h>
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#include <linux/libnvdimm.h>
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#include <asm/cacheflush.h>
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#include <asm/dma-noncoherent.h>
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void arch_wb_cache_pmem(void *addr, size_t size)
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{
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#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
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if (unlikely(noncoherent_cache_ops.wback)) {
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noncoherent_cache_ops.wback(virt_to_phys(addr), size);
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return;
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}
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#endif
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ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size);
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}
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EXPORT_SYMBOL_GPL(arch_wb_cache_pmem);
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void arch_invalidate_pmem(void *addr, size_t size)
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{
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#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
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if (unlikely(noncoherent_cache_ops.inv)) {
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noncoherent_cache_ops.inv(virt_to_phys(addr), size);
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return;
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}
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#endif
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ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size);
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}
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EXPORT_SYMBOL_GPL(arch_invalidate_pmem);
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