This patch introduces the NVMeTCP device and PF level HSI and HSI functionality in order to initialize and interact with the HW device. The patch also adds qed NVMeTCP personality. This patch is based on the qede, qedr, qedi, qedf drivers HSI. Acked-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: Dean Balandin <dbalandin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Michal Kalderon <mkalderon@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: David S. Miller <davem@davemloft.net>
589 lines
16 KiB
C
589 lines
16 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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/* QLogic qed NIC Driver
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* Copyright (c) 2015-2017 QLogic Corporation
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* Copyright (c) 2019-2020 Marvell International Ltd.
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*/
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include "qed.h"
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#include <linux/qed/qed_chain.h>
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#include "qed_cxt.h"
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#include "qed_dcbx.h"
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#include "qed_hsi.h"
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#include "qed_hw.h"
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#include "qed_int.h"
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#include "qed_reg_addr.h"
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#include "qed_sp.h"
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#include "qed_sriov.h"
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void qed_sp_destroy_request(struct qed_hwfn *p_hwfn,
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struct qed_spq_entry *p_ent)
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{
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/* qed_spq_get_entry() can either get an entry from the free_pool,
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* or, if no entries are left, allocate a new entry and add it to
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* the unlimited_pending list.
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*/
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if (p_ent->queue == &p_hwfn->p_spq->unlimited_pending)
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kfree(p_ent);
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else
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qed_spq_return_entry(p_hwfn, p_ent);
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}
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int qed_sp_init_request(struct qed_hwfn *p_hwfn,
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struct qed_spq_entry **pp_ent,
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u8 cmd, u8 protocol, struct qed_sp_init_data *p_data)
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{
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u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid;
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struct qed_spq_entry *p_ent = NULL;
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int rc;
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if (!pp_ent)
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return -ENOMEM;
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rc = qed_spq_get_entry(p_hwfn, pp_ent);
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if (rc)
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return rc;
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p_ent = *pp_ent;
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p_ent->elem.hdr.cid = cpu_to_le32(opaque_cid);
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p_ent->elem.hdr.cmd_id = cmd;
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p_ent->elem.hdr.protocol_id = protocol;
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p_ent->priority = QED_SPQ_PRIORITY_NORMAL;
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p_ent->comp_mode = p_data->comp_mode;
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p_ent->comp_done.done = 0;
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switch (p_ent->comp_mode) {
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case QED_SPQ_MODE_EBLOCK:
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p_ent->comp_cb.cookie = &p_ent->comp_done;
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break;
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case QED_SPQ_MODE_BLOCK:
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if (!p_data->p_comp_data)
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goto err;
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p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
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break;
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case QED_SPQ_MODE_CB:
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if (!p_data->p_comp_data)
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p_ent->comp_cb.function = NULL;
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else
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p_ent->comp_cb = *p_data->p_comp_data;
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break;
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default:
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DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n",
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p_ent->comp_mode);
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goto err;
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}
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DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
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"Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
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opaque_cid, cmd, protocol,
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(unsigned long)&p_ent->ramrod,
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D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK,
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QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
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"MODE_CB"));
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memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));
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return 0;
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err:
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qed_sp_destroy_request(p_hwfn, p_ent);
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return -EINVAL;
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}
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static enum tunnel_clss qed_tunn_clss_to_fw_clss(u8 type)
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{
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switch (type) {
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case QED_TUNN_CLSS_MAC_VLAN:
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return TUNNEL_CLSS_MAC_VLAN;
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case QED_TUNN_CLSS_MAC_VNI:
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return TUNNEL_CLSS_MAC_VNI;
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case QED_TUNN_CLSS_INNER_MAC_VLAN:
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return TUNNEL_CLSS_INNER_MAC_VLAN;
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case QED_TUNN_CLSS_INNER_MAC_VNI:
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return TUNNEL_CLSS_INNER_MAC_VNI;
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case QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE:
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return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE;
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default:
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return TUNNEL_CLSS_MAC_VLAN;
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}
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}
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static void
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qed_set_pf_update_tunn_mode(struct qed_tunnel_info *p_tun,
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struct qed_tunnel_info *p_src, bool b_pf_start)
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{
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if (p_src->vxlan.b_update_mode || b_pf_start)
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p_tun->vxlan.b_mode_enabled = p_src->vxlan.b_mode_enabled;
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if (p_src->l2_gre.b_update_mode || b_pf_start)
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p_tun->l2_gre.b_mode_enabled = p_src->l2_gre.b_mode_enabled;
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if (p_src->ip_gre.b_update_mode || b_pf_start)
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p_tun->ip_gre.b_mode_enabled = p_src->ip_gre.b_mode_enabled;
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if (p_src->l2_geneve.b_update_mode || b_pf_start)
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p_tun->l2_geneve.b_mode_enabled =
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p_src->l2_geneve.b_mode_enabled;
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if (p_src->ip_geneve.b_update_mode || b_pf_start)
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p_tun->ip_geneve.b_mode_enabled =
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p_src->ip_geneve.b_mode_enabled;
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}
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static void qed_set_tunn_cls_info(struct qed_tunnel_info *p_tun,
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struct qed_tunnel_info *p_src)
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{
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int type;
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p_tun->b_update_rx_cls = p_src->b_update_rx_cls;
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p_tun->b_update_tx_cls = p_src->b_update_tx_cls;
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type = qed_tunn_clss_to_fw_clss(p_src->vxlan.tun_cls);
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p_tun->vxlan.tun_cls = type;
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type = qed_tunn_clss_to_fw_clss(p_src->l2_gre.tun_cls);
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p_tun->l2_gre.tun_cls = type;
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type = qed_tunn_clss_to_fw_clss(p_src->ip_gre.tun_cls);
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p_tun->ip_gre.tun_cls = type;
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type = qed_tunn_clss_to_fw_clss(p_src->l2_geneve.tun_cls);
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p_tun->l2_geneve.tun_cls = type;
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type = qed_tunn_clss_to_fw_clss(p_src->ip_geneve.tun_cls);
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p_tun->ip_geneve.tun_cls = type;
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}
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static void qed_set_tunn_ports(struct qed_tunnel_info *p_tun,
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struct qed_tunnel_info *p_src)
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{
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p_tun->geneve_port.b_update_port = p_src->geneve_port.b_update_port;
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p_tun->vxlan_port.b_update_port = p_src->vxlan_port.b_update_port;
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if (p_src->geneve_port.b_update_port)
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p_tun->geneve_port.port = p_src->geneve_port.port;
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if (p_src->vxlan_port.b_update_port)
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p_tun->vxlan_port.port = p_src->vxlan_port.port;
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}
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static void
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__qed_set_ramrod_tunnel_param(u8 *p_tunn_cls,
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struct qed_tunn_update_type *tun_type)
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{
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*p_tunn_cls = tun_type->tun_cls;
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}
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static void
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qed_set_ramrod_tunnel_param(u8 *p_tunn_cls,
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struct qed_tunn_update_type *tun_type,
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u8 *p_update_port,
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__le16 *p_port,
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struct qed_tunn_update_udp_port *p_udp_port)
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{
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__qed_set_ramrod_tunnel_param(p_tunn_cls, tun_type);
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if (p_udp_port->b_update_port) {
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*p_update_port = 1;
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*p_port = cpu_to_le16(p_udp_port->port);
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}
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}
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static void
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qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn,
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struct qed_tunnel_info *p_src,
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struct pf_update_tunnel_config *p_tunn_cfg)
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{
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struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel;
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qed_set_pf_update_tunn_mode(p_tun, p_src, false);
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qed_set_tunn_cls_info(p_tun, p_src);
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qed_set_tunn_ports(p_tun, p_src);
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qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
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&p_tun->vxlan,
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&p_tunn_cfg->set_vxlan_udp_port_flg,
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&p_tunn_cfg->vxlan_udp_port,
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&p_tun->vxlan_port);
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qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
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&p_tun->l2_geneve,
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&p_tunn_cfg->set_geneve_udp_port_flg,
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&p_tunn_cfg->geneve_udp_port,
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&p_tun->geneve_port);
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__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
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&p_tun->ip_geneve);
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__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
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&p_tun->l2_gre);
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__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
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&p_tun->ip_gre);
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p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls;
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}
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static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct qed_tunnel_info *p_tun)
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{
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qed_set_gre_enable(p_hwfn, p_ptt, p_tun->l2_gre.b_mode_enabled,
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p_tun->ip_gre.b_mode_enabled);
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qed_set_vxlan_enable(p_hwfn, p_ptt, p_tun->vxlan.b_mode_enabled);
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qed_set_geneve_enable(p_hwfn, p_ptt, p_tun->l2_geneve.b_mode_enabled,
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p_tun->ip_geneve.b_mode_enabled);
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}
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static void qed_set_hw_tunn_mode_port(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct qed_tunnel_info *p_tunn)
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{
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if (p_tunn->vxlan_port.b_update_port)
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qed_set_vxlan_dest_port(p_hwfn, p_ptt,
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p_tunn->vxlan_port.port);
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if (p_tunn->geneve_port.b_update_port)
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qed_set_geneve_dest_port(p_hwfn, p_ptt,
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p_tunn->geneve_port.port);
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qed_set_hw_tunn_mode(p_hwfn, p_ptt, p_tunn);
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}
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static void
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qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn,
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struct qed_tunnel_info *p_src,
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struct pf_start_tunnel_config *p_tunn_cfg)
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{
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struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel;
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if (!p_src)
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return;
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qed_set_pf_update_tunn_mode(p_tun, p_src, true);
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qed_set_tunn_cls_info(p_tun, p_src);
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qed_set_tunn_ports(p_tun, p_src);
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qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
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&p_tun->vxlan,
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&p_tunn_cfg->set_vxlan_udp_port_flg,
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&p_tunn_cfg->vxlan_udp_port,
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&p_tun->vxlan_port);
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qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
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&p_tun->l2_geneve,
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&p_tunn_cfg->set_geneve_udp_port_flg,
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&p_tunn_cfg->geneve_udp_port,
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&p_tun->geneve_port);
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__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
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&p_tun->ip_geneve);
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__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
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&p_tun->l2_gre);
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__qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
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&p_tun->ip_gre);
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}
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int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct qed_tunnel_info *p_tunn,
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bool allow_npar_tx_switch)
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{
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struct outer_tag_config_struct *outer_tag_config;
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struct pf_start_ramrod_data *p_ramrod = NULL;
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u16 sb = qed_int_get_sp_sb_id(p_hwfn);
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u8 sb_index = p_hwfn->p_eq->eq_sb_index;
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struct qed_spq_entry *p_ent = NULL;
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struct qed_sp_init_data init_data;
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u8 page_cnt, i;
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int rc;
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/* update initial eq producer */
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qed_eq_prod_update(p_hwfn,
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qed_chain_get_prod_idx(&p_hwfn->p_eq->chain));
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memset(&init_data, 0, sizeof(init_data));
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init_data.cid = qed_spq_get_cid(p_hwfn);
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init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
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init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
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rc = qed_sp_init_request(p_hwfn, &p_ent,
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COMMON_RAMROD_PF_START,
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PROTOCOLID_COMMON, &init_data);
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if (rc)
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return rc;
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p_ramrod = &p_ent->ramrod.pf_start;
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p_ramrod->event_ring_sb_id = cpu_to_le16(sb);
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p_ramrod->event_ring_sb_index = sb_index;
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p_ramrod->path_id = QED_PATH_ID(p_hwfn);
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p_ramrod->dont_log_ramrods = 0;
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p_ramrod->log_type_mask = cpu_to_le16(0xf);
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if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
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p_ramrod->mf_mode = MF_OVLAN;
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else
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p_ramrod->mf_mode = MF_NPAR;
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outer_tag_config = &p_ramrod->outer_tag_config;
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outer_tag_config->outer_tag.tci = cpu_to_le16(p_hwfn->hw_info.ovlan);
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if (test_bit(QED_MF_8021Q_TAGGING, &p_hwfn->cdev->mf_bits)) {
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outer_tag_config->outer_tag.tpid = cpu_to_le16(ETH_P_8021Q);
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} else if (test_bit(QED_MF_8021AD_TAGGING, &p_hwfn->cdev->mf_bits)) {
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outer_tag_config->outer_tag.tpid = cpu_to_le16(ETH_P_8021AD);
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outer_tag_config->enable_stag_pri_change = 1;
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}
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outer_tag_config->pri_map_valid = 1;
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for (i = 0; i < QED_MAX_PFC_PRIORITIES; i++)
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outer_tag_config->inner_to_outer_pri_map[i] = i;
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/* enable_stag_pri_change should be set if port is in BD mode or,
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* UFP with Host Control mode.
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*/
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if (test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) {
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if (p_hwfn->ufp_info.pri_type == QED_UFP_PRI_OS)
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outer_tag_config->enable_stag_pri_change = 1;
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else
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outer_tag_config->enable_stag_pri_change = 0;
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outer_tag_config->outer_tag.tci |=
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cpu_to_le16(((u16)p_hwfn->ufp_info.tc << 13));
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}
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/* Place EQ address in RAMROD */
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DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
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qed_chain_get_pbl_phys(&p_hwfn->p_eq->chain));
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page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain);
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p_ramrod->event_ring_num_pages = page_cnt;
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DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
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qed_chain_get_pbl_phys(&p_hwfn->p_consq->chain));
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qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config);
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if (test_bit(QED_MF_INTER_PF_SWITCH, &p_hwfn->cdev->mf_bits))
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p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
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switch (p_hwfn->hw_info.personality) {
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case QED_PCI_ETH:
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p_ramrod->personality = PERSONALITY_ETH;
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break;
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case QED_PCI_FCOE:
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p_ramrod->personality = PERSONALITY_FCOE;
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break;
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case QED_PCI_ISCSI:
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case QED_PCI_NVMETCP:
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p_ramrod->personality = PERSONALITY_TCP_ULP;
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break;
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case QED_PCI_ETH_ROCE:
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case QED_PCI_ETH_IWARP:
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p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
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break;
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default:
|
|
DP_NOTICE(p_hwfn, "Unknown personality %d\n",
|
|
p_hwfn->hw_info.personality);
|
|
p_ramrod->personality = PERSONALITY_ETH;
|
|
}
|
|
|
|
if (p_hwfn->cdev->p_iov_info) {
|
|
struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
|
|
|
|
p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf;
|
|
p_ramrod->num_vfs = (u8) p_iov->total_vfs;
|
|
}
|
|
p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
|
|
p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
|
|
|
|
DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
|
|
"Setting event_ring_sb [id %04x index %02x], outer_tag.tci [%d]\n",
|
|
sb, sb_index, outer_tag_config->outer_tag.tci);
|
|
|
|
rc = qed_spq_post(p_hwfn, p_ent, NULL);
|
|
|
|
if (p_tunn)
|
|
qed_set_hw_tunn_mode_port(p_hwfn, p_ptt,
|
|
&p_hwfn->cdev->tunnel);
|
|
|
|
return rc;
|
|
}
|
|
|
|
int qed_sp_pf_update(struct qed_hwfn *p_hwfn)
|
|
{
|
|
struct qed_spq_entry *p_ent = NULL;
|
|
struct qed_sp_init_data init_data;
|
|
int rc;
|
|
|
|
/* Get SPQ entry */
|
|
memset(&init_data, 0, sizeof(init_data));
|
|
init_data.cid = qed_spq_get_cid(p_hwfn);
|
|
init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
|
|
init_data.comp_mode = QED_SPQ_MODE_CB;
|
|
|
|
rc = qed_sp_init_request(p_hwfn, &p_ent,
|
|
COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
|
|
&init_data);
|
|
if (rc)
|
|
return rc;
|
|
|
|
qed_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
|
|
&p_ent->ramrod.pf_update);
|
|
|
|
return qed_spq_post(p_hwfn, p_ent, NULL);
|
|
}
|
|
|
|
int qed_sp_pf_update_ufp(struct qed_hwfn *p_hwfn)
|
|
{
|
|
struct qed_spq_entry *p_ent = NULL;
|
|
struct qed_sp_init_data init_data;
|
|
int rc;
|
|
|
|
if (p_hwfn->ufp_info.pri_type == QED_UFP_PRI_UNKNOWN) {
|
|
DP_INFO(p_hwfn, "Invalid priority type %d\n",
|
|
p_hwfn->ufp_info.pri_type);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Get SPQ entry */
|
|
memset(&init_data, 0, sizeof(init_data));
|
|
init_data.cid = qed_spq_get_cid(p_hwfn);
|
|
init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
|
|
init_data.comp_mode = QED_SPQ_MODE_CB;
|
|
|
|
rc = qed_sp_init_request(p_hwfn, &p_ent,
|
|
COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
|
|
&init_data);
|
|
if (rc)
|
|
return rc;
|
|
|
|
p_ent->ramrod.pf_update.update_enable_stag_pri_change = true;
|
|
if (p_hwfn->ufp_info.pri_type == QED_UFP_PRI_OS)
|
|
p_ent->ramrod.pf_update.enable_stag_pri_change = 1;
|
|
else
|
|
p_ent->ramrod.pf_update.enable_stag_pri_change = 0;
|
|
|
|
return qed_spq_post(p_hwfn, p_ent, NULL);
|
|
}
|
|
|
|
/* Set pf update ramrod command params */
|
|
int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn,
|
|
struct qed_ptt *p_ptt,
|
|
struct qed_tunnel_info *p_tunn,
|
|
enum spq_mode comp_mode,
|
|
struct qed_spq_comp_cb *p_comp_data)
|
|
{
|
|
struct qed_spq_entry *p_ent = NULL;
|
|
struct qed_sp_init_data init_data;
|
|
int rc;
|
|
|
|
if (IS_VF(p_hwfn->cdev))
|
|
return qed_vf_pf_tunnel_param_update(p_hwfn, p_tunn);
|
|
|
|
if (!p_tunn)
|
|
return -EINVAL;
|
|
|
|
/* Get SPQ entry */
|
|
memset(&init_data, 0, sizeof(init_data));
|
|
init_data.cid = qed_spq_get_cid(p_hwfn);
|
|
init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
|
|
init_data.comp_mode = comp_mode;
|
|
init_data.p_comp_data = p_comp_data;
|
|
|
|
rc = qed_sp_init_request(p_hwfn, &p_ent,
|
|
COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
|
|
&init_data);
|
|
if (rc)
|
|
return rc;
|
|
|
|
qed_tunn_set_pf_update_params(p_hwfn, p_tunn,
|
|
&p_ent->ramrod.pf_update.tunnel_config);
|
|
|
|
rc = qed_spq_post(p_hwfn, p_ent, NULL);
|
|
if (rc)
|
|
return rc;
|
|
|
|
qed_set_hw_tunn_mode_port(p_hwfn, p_ptt, &p_hwfn->cdev->tunnel);
|
|
|
|
return rc;
|
|
}
|
|
|
|
int qed_sp_pf_stop(struct qed_hwfn *p_hwfn)
|
|
{
|
|
struct qed_spq_entry *p_ent = NULL;
|
|
struct qed_sp_init_data init_data;
|
|
int rc;
|
|
|
|
/* Get SPQ entry */
|
|
memset(&init_data, 0, sizeof(init_data));
|
|
init_data.cid = qed_spq_get_cid(p_hwfn);
|
|
init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
|
|
init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
|
|
|
|
rc = qed_sp_init_request(p_hwfn, &p_ent,
|
|
COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
|
|
&init_data);
|
|
if (rc)
|
|
return rc;
|
|
|
|
return qed_spq_post(p_hwfn, p_ent, NULL);
|
|
}
|
|
|
|
int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn)
|
|
{
|
|
struct qed_spq_entry *p_ent = NULL;
|
|
struct qed_sp_init_data init_data;
|
|
int rc;
|
|
|
|
/* Get SPQ entry */
|
|
memset(&init_data, 0, sizeof(init_data));
|
|
init_data.cid = qed_spq_get_cid(p_hwfn);
|
|
init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
|
|
init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
|
|
|
|
rc = qed_sp_init_request(p_hwfn, &p_ent,
|
|
COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
|
|
&init_data);
|
|
if (rc)
|
|
return rc;
|
|
|
|
return qed_spq_post(p_hwfn, p_ent, NULL);
|
|
}
|
|
|
|
int qed_sp_pf_update_stag(struct qed_hwfn *p_hwfn)
|
|
{
|
|
struct qed_spq_entry *p_ent = NULL;
|
|
struct qed_sp_init_data init_data;
|
|
int rc;
|
|
|
|
/* Get SPQ entry */
|
|
memset(&init_data, 0, sizeof(init_data));
|
|
init_data.cid = qed_spq_get_cid(p_hwfn);
|
|
init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
|
|
init_data.comp_mode = QED_SPQ_MODE_CB;
|
|
|
|
rc = qed_sp_init_request(p_hwfn, &p_ent,
|
|
COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
|
|
&init_data);
|
|
if (rc)
|
|
return rc;
|
|
|
|
p_ent->ramrod.pf_update.update_mf_vlan_flag = true;
|
|
p_ent->ramrod.pf_update.mf_vlan = cpu_to_le16(p_hwfn->hw_info.ovlan);
|
|
if (test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits))
|
|
p_ent->ramrod.pf_update.mf_vlan |=
|
|
cpu_to_le16(((u16)p_hwfn->ufp_info.tc << 13));
|
|
|
|
return qed_spq_post(p_hwfn, p_ent, NULL);
|
|
}
|