241527bb84
Cleanups of RISC-V SiFive and Microchip DTSes with dtschema. These are few minor fixes to make DTSes pass the dtschema, without actual functional effect. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmFxLQwQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD1/UGD/4vFvmJdbVPd2tDu81qBwrBx13NrAGj2jlM 6+ZfOzxCZEFd0e+uvhL39f0rm9G7E/TIHtsAc0vL9+InoyByy1UjkCtgDgBAzqPq LNmL/QqRsWYivIs7kytnl2Q0b4GS4qflJ9YBe7KHr0apoTFYwIF9pAOCnllG5XG4 0N94CK/ucWJgkE8R11Zt0cVLBp3ZDJ+rRc9Afqhw/kTznzdVNxjL7h0a1J0FlfH2 vFDzP34YdUJt5k0eWeu1ZFBpcN5u45/zE/TtiI8hqsehy2+opuiWocKv2duoJZ2F X48+Jtw3dahq7KbZPVOnxx/nbEDn4/Bsj/B8Mrqv+wk5BQMRl7L0x2LpbFNJoAB2 TDsTr19dvCi09C6eA8aVM/FSLeeuexeeJ9U4luthHZWHjEgA94lGSkCHyBlKZGzG ro7y25q0lDNBdhxnYZK5PHRJ7sVnSRbMz27cCVQuG6zlSlC8miwNxvTDdscQS5OS 9sylhsSjvSlkOUNZ9t2SgjcBgX55Qap+TvTIjaOL3rFwwbOzEPPw71pI2OYWy8XD piE3wc8zZwUuMHa1BjsE9o0Jy3X3vGJyrY76tId93S7JVOpZB/xsEhtm7SRXOcHm kmM1pDOC6OvY+JRhFEohSVBszLhxH2Qm+v7A8z0Ijt1Ellz6kljKYwQLaSp6KCOK DvRlr/SstQ== =4+vY -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJHBAABCgAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmFxhioTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiZgCD/9x9h4aaki1atNgNNW+n+ZACn3pBuBO r2mSoUzx1Zvfex2CHQq/2jZce7p+gtVaFuroD3QgySyRcf3FUZwF4Crmg6DotQKO TuAzLPCUZAd2HjgvpsgCY8HLzFu7ZRPLtwzph/UaQ6fIVKLF1hbyg/3LMkG7wxUR Rxh7h7NTAELlmQjc2SvTRGEX8DyB1HGRereJbNb8DjXjS2+Iezyt5VePwiEME5Z0 Bmaq1jhBBcmI7IYPxhIn4CDmOY3Xo34ArITwPuOD0eb/kppVal5Tym761aXHnCNZ r2/k/p/lXLa5W4nDEDuldM8HwR/KvUgquEYraqw6f1/4u0XRuuk3jifWSHRWkxNj QsxyqTqsl44AnNe5vTf2QiuDbGk0Y3C79wmlC4lakcxohUjjwu3EHOdYypyu52W5 1u4kkVQxVkKCLoJO6/ZBw/BsOk51tXffcHd9SwtKfj1QzJa3JBYgSwDigq37cNQo fsv1k0mrZFDWk1fYSGwvzrwSkF4qckLjp0aiSc/0x5YpvZqUNiLpXsWj1eRx/OfM rHgVtkfBhsY2ddOflNkXnYlyFRH4twIAknD3dLoDhotvRYMceU28Y2zRjbJGIWFt SOXKhDfZRiPYmyMeMh9wUZK4yrdpcSdb8MbTr14UeDhSn8ZnKXberfs4DaXMEsu7 x90g5jAP8NJ3ag== =8DbL -----END PGP SIGNATURE----- Merge tag 'riscv-sifive-dt-5.16' of git://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux into for-next RISC-V DTS changes for v5.16 Cleanups of RISC-V SiFive and Microchip DTSes with dtschema. These are few minor fixes to make DTSes pass the dtschema, without actual functional effect. * tag 'riscv-sifive-dt-5.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux: riscv: dts: sifive: add missing compatible for plic riscv: dts: microchip: add missing compatibles for clint and plic riscv: dts: sifive: drop duplicated nodes and properties in sifive riscv: dts: sifive: fix Unleashed board compatible riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible
303 lines
7.1 KiB
Text
303 lines
7.1 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020 Microchip Technology Inc */
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Microchip PolarFire SoC";
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compatible = "microchip,mpfs";
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chosen {
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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clock-frequency = <0>;
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compatible = "sifive,e51", "sifive,rocket0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <16384>;
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reg = <0>;
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riscv,isa = "rv64imac";
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status = "disabled";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@1 {
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clock-frequency = <0>;
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <1>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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status = "okay";
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@2 {
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clock-frequency = <0>;
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <2>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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status = "okay";
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cpu2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@3 {
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clock-frequency = <0>;
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <3>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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status = "okay";
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cpu3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@4 {
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clock-frequency = <0>;
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <4>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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status = "okay";
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cpu4_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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cache-controller@2010000 {
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compatible = "sifive,fu540-c000-ccache", "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <1024>;
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cache-size = <2097152>;
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cache-unified;
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interrupt-parent = <&plic>;
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interrupts = <1 2 3>;
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reg = <0x0 0x2010000 0x0 0x1000>;
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};
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clint@2000000 {
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compatible = "sifive,fu540-c000-clint", "sifive,clint0";
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reg = <0x0 0x2000000 0x0 0xC000>;
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interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
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&cpu1_intc 3 &cpu1_intc 7
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&cpu2_intc 3 &cpu2_intc 7
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&cpu3_intc 3 &cpu3_intc 7
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&cpu4_intc 3 &cpu4_intc 7>;
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};
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plic: interrupt-controller@c000000 {
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#interrupt-cells = <1>;
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compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
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reg = <0x0 0xc000000 0x0 0x4000000>;
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riscv,ndev = <186>;
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interrupt-controller;
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interrupts-extended = <&cpu0_intc 11
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&cpu1_intc 11 &cpu1_intc 9
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&cpu2_intc 11 &cpu2_intc 9
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&cpu3_intc 11 &cpu3_intc 9
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&cpu4_intc 11 &cpu4_intc 9>;
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};
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dma@3000000 {
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compatible = "sifive,fu540-c000-pdma";
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reg = <0x0 0x3000000 0x0 0x8000>;
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interrupt-parent = <&plic>;
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interrupts = <23 24 25 26 27 28 29 30>;
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#dma-cells = <1>;
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};
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refclk: refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <600000000>;
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clock-output-names = "msspllclk";
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};
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clkcfg: clkcfg@20002000 {
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compatible = "microchip,mpfs-clkcfg";
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reg = <0x0 0x20002000 0x0 0x1000>;
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reg-names = "mss_sysreg";
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clocks = <&refclk>;
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#clock-cells = <1>;
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clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
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"mac0", "mac1", "mmc", "timer", /* 4-7 */
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"mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
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"mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
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"i2c1", "can0", "can1", "usb", /* 16-19 */
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"rsvd", "rtc", "qspi", "gpio0", /* 20-23 */
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"gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */
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"fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */
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};
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serial0: serial@20000000 {
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compatible = "ns16550a";
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reg = <0x0 0x20000000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <90>;
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current-speed = <115200>;
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clocks = <&clkcfg 8>;
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status = "disabled";
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};
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serial1: serial@20100000 {
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compatible = "ns16550a";
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reg = <0x0 0x20100000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <91>;
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current-speed = <115200>;
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clocks = <&clkcfg 9>;
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status = "disabled";
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};
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serial2: serial@20102000 {
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compatible = "ns16550a";
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reg = <0x0 0x20102000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <92>;
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current-speed = <115200>;
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clocks = <&clkcfg 10>;
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status = "disabled";
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};
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serial3: serial@20104000 {
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compatible = "ns16550a";
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reg = <0x0 0x20104000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <93>;
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current-speed = <115200>;
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clocks = <&clkcfg 11>;
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status = "disabled";
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};
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/* Common node entry for emmc/sd */
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mmc: mmc@20008000 {
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compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
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reg = <0x0 0x20008000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <88 89>;
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clocks = <&clkcfg 6>;
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max-frequency = <200000000>;
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status = "disabled";
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};
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emac0: ethernet@20110000 {
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compatible = "cdns,macb";
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reg = <0x0 0x20110000 0x0 0x2000>;
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interrupt-parent = <&plic>;
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interrupts = <64 65 66 67>;
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&clkcfg 4>, <&clkcfg 2>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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emac1: ethernet@20112000 {
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compatible = "cdns,macb";
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reg = <0x0 0x20112000 0x0 0x2000>;
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interrupt-parent = <&plic>;
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interrupts = <70 71 72 73>;
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&clkcfg 5>, <&clkcfg 2>;
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status = "disabled";
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clock-names = "pclk", "hclk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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