4cd8c3152e
Mailbox region configuration has some changes on CN10K platform from OcteonTX2(CN9XX) platform. On CN10K platform: The DRAM region allocated to PF is enumerated as PF BAR4 memory. PF BAR4 contains AF-PF mbox region followed by its VFs mbox region. AF-PF mbox region base address is configured at RVU_AF_PFX_BAR4_ADDR PF-VF mailbox base address is configured at RVU_PF(x)_VF_MBOX_ADDR = RVU_AF_PF()_BAR4_ADDR+64KB. PF access its mbox region via BAR4, whereas VF accesses PF-VF DRAM mailboxes via BAR2 indirect access. On CN9XX platform: Mailbox region in DRAM is divided into two parts AF-PF mbox region and PF-VF mbox region i.e all PFs mbox region is contiguous similarly all VFs. The base address of the AF-PF mbox region is configured at RVU_AF_PF_BAR4_ADDR. AF-PF1 mbox address can be calculated as RVU_AF_PF_BAR4_ADDR * mbox size. This patch changes mbox initialization to support both CN9XX and CN10K platform. This patch also removes platform specific name from the PF/VF driver name to make it appropriate for all supported platforms. Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
63 lines
1.8 KiB
C
63 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only
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* Copyright (C) 2020 Marvell.
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*/
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#ifndef __OTX2_CPTPF_H
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#define __OTX2_CPTPF_H
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#include "otx2_cpt_common.h"
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#include "otx2_cptpf_ucode.h"
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#include "otx2_cptlf.h"
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struct otx2_cptpf_dev;
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struct otx2_cptvf_info {
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struct otx2_cptpf_dev *cptpf; /* PF pointer this VF belongs to */
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struct work_struct vfpf_mbox_work;
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struct pci_dev *vf_dev;
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int vf_id;
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int intr_idx;
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};
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struct cptpf_flr_work {
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struct work_struct work;
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struct otx2_cptpf_dev *pf;
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};
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struct otx2_cptpf_dev {
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void __iomem *reg_base; /* CPT PF registers start address */
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void __iomem *afpf_mbox_base; /* PF-AF mbox start address */
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void __iomem *vfpf_mbox_base; /* VF-PF mbox start address */
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struct pci_dev *pdev; /* PCI device handle */
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struct otx2_cptvf_info vf[OTX2_CPT_MAX_VFS_NUM];
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struct otx2_cpt_eng_grps eng_grps;/* Engine groups information */
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struct otx2_cptlfs_info lfs; /* CPT LFs attached to this PF */
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/* HW capabilities for each engine type */
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union otx2_cpt_eng_caps eng_caps[OTX2_CPT_MAX_ENG_TYPES];
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bool is_eng_caps_discovered;
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/* AF <=> PF mbox */
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struct otx2_mbox afpf_mbox;
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struct work_struct afpf_mbox_work;
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struct workqueue_struct *afpf_mbox_wq;
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/* VF <=> PF mbox */
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struct otx2_mbox vfpf_mbox;
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struct workqueue_struct *vfpf_mbox_wq;
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struct workqueue_struct *flr_wq;
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struct cptpf_flr_work *flr_work;
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unsigned long cap_flag;
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u8 pf_id; /* RVU PF number */
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u8 max_vfs; /* Maximum number of VFs supported by CPT */
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u8 enabled_vfs; /* Number of enabled VFs */
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u8 kvf_limits; /* Kernel crypto limits */
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bool has_cpt1;
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};
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irqreturn_t otx2_cptpf_afpf_mbox_intr(int irq, void *arg);
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void otx2_cptpf_afpf_mbox_handler(struct work_struct *work);
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irqreturn_t otx2_cptpf_vfpf_mbox_intr(int irq, void *arg);
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void otx2_cptpf_vfpf_mbox_handler(struct work_struct *work);
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#endif /* __OTX2_CPTPF_H */
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