216d56c5da
This feature hands over the control of HW RC6 to the GuC. GuC decides when to put HW into RC6 based on it's internal busyness algorithms. GuCRC needs GuC submission to be enabled, and only supported on Gen12+ for now. When GuCRC is enabled, do not set HW RC6. Use a H2G message to tell GuC to enable GuCRC. When disabling RC6, tell GuC to revert RC6 control back to KMD. KMD is still responsible for enabling everything related to Coarse Power Gating though. v2: Address comments (Michal W) v3: Don't set hysterisis values when GuCRC is used (Matt Roper) v4: checkpatch() Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210730202119.23810-15-vinay.belgaumkar@intel.com
80 lines
1.6 KiB
C
80 lines
1.6 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2021 Intel Corporation
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*/
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#include "intel_guc_rc.h"
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#include "gt/intel_gt.h"
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#include "i915_drv.h"
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static bool __guc_rc_supported(struct intel_guc *guc)
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{
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/* GuC RC is unavailable for pre-Gen12 */
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return guc->submission_supported &&
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GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
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}
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static bool __guc_rc_selected(struct intel_guc *guc)
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{
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if (!intel_guc_rc_is_supported(guc))
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return false;
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return guc->submission_selected;
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}
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void intel_guc_rc_init_early(struct intel_guc *guc)
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{
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guc->rc_supported = __guc_rc_supported(guc);
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guc->rc_selected = __guc_rc_selected(guc);
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}
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static int guc_action_control_gucrc(struct intel_guc *guc, bool enable)
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{
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u32 rc_mode = enable ? INTEL_GUCRC_FIRMWARE_CONTROL :
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INTEL_GUCRC_HOST_CONTROL;
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u32 action[] = {
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INTEL_GUC_ACTION_SETUP_PC_GUCRC,
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rc_mode
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};
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int ret;
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ret = intel_guc_send(guc, action, ARRAY_SIZE(action));
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ret = ret > 0 ? -EPROTO : ret;
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return ret;
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}
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static int __guc_rc_control(struct intel_guc *guc, bool enable)
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{
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struct intel_gt *gt = guc_to_gt(guc);
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struct drm_device *drm = &guc_to_gt(guc)->i915->drm;
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int ret;
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if (!intel_uc_uses_guc_rc(>->uc))
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return -EOPNOTSUPP;
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if (!intel_guc_is_ready(guc))
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return -EINVAL;
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ret = guc_action_control_gucrc(guc, enable);
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if (ret) {
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drm_err(drm, "Failed to %s GuC RC (%pe)\n",
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enabledisable(enable), ERR_PTR(ret));
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return ret;
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}
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drm_info(>->i915->drm, "GuC RC: %s\n",
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enableddisabled(enable));
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return 0;
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}
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int intel_guc_rc_enable(struct intel_guc *guc)
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{
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return __guc_rc_control(guc, true);
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}
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int intel_guc_rc_disable(struct intel_guc *guc)
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{
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return __guc_rc_control(guc, false);
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}
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