Create an environment for CXL plumbing unit tests. Especially when it comes to an algorithm for HDM Decoder (Host-managed Device Memory Decoder) programming, the availability of an in-kernel-tree emulation environment for CXL configuration complexity and corner cases speeds development and deters regressions. The approach taken mirrors what was done for tools/testing/nvdimm/. I.e. an external module, cxl_test.ko built out of the tools/testing/cxl/ directory, provides mock implementations of kernel APIs and kernel objects to simulate a real world device hierarchy. One feedback for the tools/testing/nvdimm/ proposal was "why not do this in QEMU?". In fact, the CXL development community has developed a QEMU model for CXL [1]. However, there are a few blocking issues that keep QEMU from being a tight fit for topology + provisioning unit tests: 1/ The QEMU community has yet to show interest in merging any of this support that has had patches on the list since November 2020. So, testing CXL to date involves building custom QEMU with out-of-tree patches. 2/ CXL mechanisms like cross-host-bridge interleave do not have a clear path to be emulated by QEMU without major infrastructure work. This is easier to achieve with the alloc_mock_res() approach taken in this patch to shortcut-define emulated system physical address ranges with interleave behavior. The QEMU enabling has been critical to get the driver off the ground, and may still move forward, but it does not address the ongoing needs of a regression testing environment and test driven development. This patch adds an ACPI CXL Platform definition with emulated CXL multi-ported host-bridges. A follow on patch adds emulated memory expander devices. Acked-by: Ben Widawsky <ben.widawsky@intel.com> Reported-by: Vishal Verma <vishal.l.verma@intel.com> Link: https://lore.kernel.org/r/20210202005948.241655-1-ben.widawsky@intel.com [1] Link: https://lore.kernel.org/r/163164680798.2831381.838684634806668012.stgit@dwillia2-desk3.amr.corp.intel.com Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
171 lines
3.8 KiB
C
171 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//Copyright(c) 2021 Intel Corporation. All rights reserved.
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#include <linux/libnvdimm.h>
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#include <linux/rculist.h>
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#include <linux/device.h>
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#include <linux/export.h>
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#include <linux/acpi.h>
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#include <linux/pci.h>
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#include "mock.h"
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static LIST_HEAD(mock);
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void register_cxl_mock_ops(struct cxl_mock_ops *ops)
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{
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list_add_rcu(&ops->list, &mock);
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}
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EXPORT_SYMBOL_GPL(register_cxl_mock_ops);
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static DEFINE_SRCU(cxl_mock_srcu);
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void unregister_cxl_mock_ops(struct cxl_mock_ops *ops)
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{
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list_del_rcu(&ops->list);
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synchronize_srcu(&cxl_mock_srcu);
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}
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EXPORT_SYMBOL_GPL(unregister_cxl_mock_ops);
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struct cxl_mock_ops *get_cxl_mock_ops(int *index)
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{
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*index = srcu_read_lock(&cxl_mock_srcu);
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return list_first_or_null_rcu(&mock, struct cxl_mock_ops, list);
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}
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EXPORT_SYMBOL_GPL(get_cxl_mock_ops);
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void put_cxl_mock_ops(int index)
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{
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srcu_read_unlock(&cxl_mock_srcu, index);
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}
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EXPORT_SYMBOL_GPL(put_cxl_mock_ops);
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bool __wrap_is_acpi_device_node(const struct fwnode_handle *fwnode)
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{
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struct acpi_device *adev =
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container_of(fwnode, struct acpi_device, fwnode);
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int index;
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struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
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bool retval = false;
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if (ops)
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retval = ops->is_mock_adev(adev);
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if (!retval)
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retval = is_acpi_device_node(fwnode);
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put_cxl_mock_ops(index);
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return retval;
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}
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EXPORT_SYMBOL(__wrap_is_acpi_device_node);
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acpi_status __wrap_acpi_get_table(char *signature, u32 instance,
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struct acpi_table_header **out_table)
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{
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int index;
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struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
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acpi_status status;
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if (ops)
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status = ops->acpi_get_table(signature, instance, out_table);
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else
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status = acpi_get_table(signature, instance, out_table);
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put_cxl_mock_ops(index);
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return status;
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}
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EXPORT_SYMBOL(__wrap_acpi_get_table);
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void __wrap_acpi_put_table(struct acpi_table_header *table)
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{
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int index;
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struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
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if (ops)
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ops->acpi_put_table(table);
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else
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acpi_put_table(table);
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put_cxl_mock_ops(index);
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}
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EXPORT_SYMBOL(__wrap_acpi_put_table);
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acpi_status __wrap_acpi_evaluate_integer(acpi_handle handle,
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acpi_string pathname,
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struct acpi_object_list *arguments,
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unsigned long long *data)
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{
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int index;
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struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
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acpi_status status;
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if (ops)
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status = ops->acpi_evaluate_integer(handle, pathname, arguments,
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data);
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else
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status = acpi_evaluate_integer(handle, pathname, arguments,
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data);
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put_cxl_mock_ops(index);
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return status;
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}
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EXPORT_SYMBOL(__wrap_acpi_evaluate_integer);
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struct acpi_pci_root *__wrap_acpi_pci_find_root(acpi_handle handle)
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{
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int index;
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struct acpi_pci_root *root;
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struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
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if (ops)
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root = ops->acpi_pci_find_root(handle);
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else
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root = acpi_pci_find_root(handle);
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put_cxl_mock_ops(index);
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return root;
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}
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EXPORT_SYMBOL_GPL(__wrap_acpi_pci_find_root);
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void __wrap_pci_walk_bus(struct pci_bus *bus,
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int (*cb)(struct pci_dev *, void *), void *userdata)
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{
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int index;
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struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
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if (ops && ops->is_mock_bus(bus)) {
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int rc, i;
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/*
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* Simulate 2 root ports per host-bridge and no
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* depth recursion.
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*/
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for (i = 0; i < 2; i++) {
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rc = cb((struct pci_dev *) ops->mock_port(bus, i),
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userdata);
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if (rc)
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break;
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}
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} else
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pci_walk_bus(bus, cb, userdata);
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put_cxl_mock_ops(index);
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}
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EXPORT_SYMBOL_GPL(__wrap_pci_walk_bus);
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struct nvdimm_bus *
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__wrap_nvdimm_bus_register(struct device *dev,
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struct nvdimm_bus_descriptor *nd_desc)
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{
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int index;
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struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
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if (ops && ops->is_mock_dev(dev->parent->parent))
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nd_desc->provider_name = "cxl_test";
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put_cxl_mock_ops(index);
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return nvdimm_bus_register(dev, nd_desc);
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}
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EXPORT_SYMBOL_GPL(__wrap_nvdimm_bus_register);
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MODULE_LICENSE("GPL v2");
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