e0f85f4690
Shader read, write and atomic memory operations can be alerted to the debugger as an address watch exception. Allow the debugger to pass in a watch point to a particular memory address per device. Note that there exists only 4 watch points per devices to date, so have the KFD keep track of what watch points are allocated or not. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
55 lines
2.5 KiB
C
55 lines
2.5 KiB
C
/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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uint32_t kgd_gfx_v10_enable_debug_trap(struct amdgpu_device *adev,
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bool restore_dbg_registers,
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uint32_t vmid);
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uint32_t kgd_gfx_v10_disable_debug_trap(struct amdgpu_device *adev,
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bool keep_trap_enabled,
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uint32_t vmid);
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int kgd_gfx_v10_validate_trap_override_request(struct amdgpu_device *adev,
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uint32_t trap_override,
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uint32_t *trap_mask_supported);
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uint32_t kgd_gfx_v10_set_wave_launch_trap_override(struct amdgpu_device *adev,
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uint32_t vmid,
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uint32_t trap_override,
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uint32_t trap_mask_bits,
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uint32_t trap_mask_request,
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uint32_t *trap_mask_prev,
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uint32_t kfd_dbg_trap_cntl_prev);
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uint32_t kgd_gfx_v10_set_wave_launch_mode(struct amdgpu_device *adev,
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uint8_t wave_launch_mode,
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uint32_t vmid);
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uint32_t kgd_gfx_v10_set_address_watch(struct amdgpu_device *adev,
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uint64_t watch_address,
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uint32_t watch_address_mask,
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uint32_t watch_id,
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uint32_t watch_mode,
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uint32_t debug_vmid);
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uint32_t kgd_gfx_v10_clear_address_watch(struct amdgpu_device *adev,
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uint32_t watch_id);
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void kgd_gfx_v10_get_iq_wait_times(struct amdgpu_device *adev, uint32_t *wait_times);
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void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev,
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uint32_t wait_times,
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uint32_t grace_period,
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uint32_t *reg_offset,
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uint32_t *reg_data);
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