[why] dc_destroy should only clean up SW, this is because GPUs may be removed before driver unload, leading to HW to be unavailable. [how] remove GPIO close as part of GPIO destroy, this is unnecessary because GPIO is not shared, and GPIOs are generally closed after being opened Add tracking to HW access during destructor to make future issues easier to pinpoint, and block access to prevent hangs. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
494 lines
14 KiB
C
494 lines
14 KiB
C
/*
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* Copyright 2012-16 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <linux/slab.h>
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#include "dce_abm.h"
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#include "dm_services.h"
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#include "reg_helper.h"
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#include "fixed31_32.h"
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#include "dc.h"
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#include "atom.h"
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#define TO_DCE_ABM(abm)\
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container_of(abm, struct dce_abm, base)
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#define REG(reg) \
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(abm_dce->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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abm_dce->abm_shift->field_name, abm_dce->abm_mask->field_name
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#define DC_LOGGER \
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abm->ctx->logger
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#define CTX \
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abm_dce->base.ctx
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#define MCP_ABM_LEVEL_SET 0x65
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#define MCP_ABM_PIPE_SET 0x66
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#define MCP_BL_SET 0x67
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#define MCP_DISABLE_ABM_IMMEDIATELY 255
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static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id)
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{
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struct dce_abm *abm_dce = TO_DCE_ABM(abm);
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uint32_t rampingBoundary = 0xFFFF;
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if (abm->dmcu_is_running == false)
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return true;
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REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
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1, 80000);
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/* set ramping boundary */
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REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary);
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/* setDMCUParam_Pipe */
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REG_UPDATE_2(MASTER_COMM_CMD_REG,
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MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET,
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MASTER_COMM_CMD_REG_BYTE1, controller_id);
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/* notifyDMCUMsg */
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REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
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return true;
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}
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static unsigned int calculate_16_bit_backlight_from_pwm(struct dce_abm *abm_dce)
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{
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uint64_t current_backlight;
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uint32_t round_result;
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uint32_t pwm_period_cntl, bl_period, bl_int_count;
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uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en;
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uint32_t bl_period_mask, bl_pwm_mask;
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pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);
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REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
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REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
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bl_pwm_cntl = REG_READ(BL_PWM_CNTL);
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REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm));
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REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);
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if (bl_int_count == 0)
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bl_int_count = 16;
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bl_period_mask = (1 << bl_int_count) - 1;
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bl_period &= bl_period_mask;
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bl_pwm_mask = bl_period_mask << (16 - bl_int_count);
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if (fractional_duty_cycle_en == 0)
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bl_pwm &= bl_pwm_mask;
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else
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bl_pwm &= 0xFFFF;
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current_backlight = bl_pwm << (1 + bl_int_count);
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if (bl_period == 0)
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bl_period = 0xFFFF;
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current_backlight = div_u64(current_backlight, bl_period);
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current_backlight = (current_backlight + 1) >> 1;
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current_backlight = (uint64_t)(current_backlight) * bl_period;
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round_result = (uint32_t)(current_backlight & 0xFFFFFFFF);
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round_result = (round_result >> (bl_int_count-1)) & 1;
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current_backlight >>= bl_int_count;
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current_backlight += round_result;
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return (uint32_t)(current_backlight);
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}
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static void driver_set_backlight_level(struct dce_abm *abm_dce,
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uint32_t backlight_pwm_u16_16)
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{
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uint32_t backlight_16bit;
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uint32_t masked_pwm_period;
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uint8_t bit_count;
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uint64_t active_duty_cycle;
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uint32_t pwm_period_bitcnt;
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/*
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* 1. Find 16 bit backlight active duty cycle, where 0 <= backlight
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* active duty cycle <= backlight period
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*/
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/* 1.1 Apply bitmask for backlight period value based on value of BITCNT
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*/
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REG_GET_2(BL_PWM_PERIOD_CNTL,
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BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt,
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BL_PWM_PERIOD, &masked_pwm_period);
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if (pwm_period_bitcnt == 0)
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bit_count = 16;
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else
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bit_count = pwm_period_bitcnt;
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/* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */
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masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1);
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/* 1.2 Calculate integer active duty cycle required upper 16 bits
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* contain integer component, lower 16 bits contain fractional component
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* of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24
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*/
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active_duty_cycle = backlight_pwm_u16_16 * masked_pwm_period;
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/* 1.3 Calculate 16 bit active duty cycle from integer and fractional
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* components shift by bitCount then mask 16 bits and add rounding bit
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* from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0
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*/
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backlight_16bit = active_duty_cycle >> bit_count;
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backlight_16bit &= 0xFFFF;
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backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1;
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/*
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* 2. Program register with updated value
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*/
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/* 2.1 Lock group 2 backlight registers */
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REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK,
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BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1,
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BL_PWM_GRP1_REG_LOCK, 1);
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// 2.2 Write new active duty cycle
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REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit);
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/* 2.3 Unlock group 2 backlight registers */
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REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
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BL_PWM_GRP1_REG_LOCK, 0);
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/* 3 Wait for pending bit to be cleared */
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REG_WAIT(BL_PWM_GRP1_REG_LOCK,
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BL_PWM_GRP1_REG_UPDATE_PENDING, 0,
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1, 10000);
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}
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static void dmcu_set_backlight_level(
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struct dce_abm *abm_dce,
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uint32_t backlight_pwm_u16_16,
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uint32_t frame_ramp,
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uint32_t controller_id)
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{
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unsigned int backlight_8_bit = 0;
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uint32_t s2;
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if (backlight_pwm_u16_16 & 0x10000)
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// Check for max backlight condition
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backlight_8_bit = 0xFF;
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else
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// Take MSB of fractional part since backlight is not max
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backlight_8_bit = (backlight_pwm_u16_16 >> 8) & 0xFF;
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dce_abm_set_pipe(&abm_dce->base, controller_id);
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/* waitDMCUReadyForCmd */
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REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
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0, 1, 80000);
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/* setDMCUParam_BL */
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REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_pwm_u16_16);
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/* write ramp */
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if (controller_id == 0)
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frame_ramp = 0;
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REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp);
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/* setDMCUParam_Cmd */
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REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET);
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/* notifyDMCUMsg */
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REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
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/* UpdateRequestedBacklightLevel */
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s2 = REG_READ(BIOS_SCRATCH_2);
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s2 &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
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backlight_8_bit &= (ATOM_S2_CURRENT_BL_LEVEL_MASK >>
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ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
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s2 |= (backlight_8_bit << ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
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REG_WRITE(BIOS_SCRATCH_2, s2);
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/* waitDMCUReadyForCmd */
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REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
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0, 1, 80000);
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}
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static void dce_abm_init(struct abm *abm)
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{
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struct dce_abm *abm_dce = TO_DCE_ABM(abm);
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unsigned int backlight = calculate_16_bit_backlight_from_pwm(abm_dce);
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REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103);
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REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101);
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REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103);
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REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101);
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REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101);
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REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0,
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ABM1_HG_NUM_OF_BINS_SEL, 0,
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ABM1_HG_VMAX_SEL, 1,
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ABM1_HG_BIN_BITWIDTH_SIZE_SEL, 0);
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REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0,
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ABM1_IPCSC_COEFF_SEL_R, 2,
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ABM1_IPCSC_COEFF_SEL_G, 4,
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ABM1_IPCSC_COEFF_SEL_B, 2);
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REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL,
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BL1_PWM_CURRENT_ABM_LEVEL, backlight);
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REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL,
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BL1_PWM_TARGET_ABM_LEVEL, backlight);
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REG_UPDATE(BL1_PWM_USER_LEVEL,
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BL1_PWM_USER_LEVEL, backlight);
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REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES,
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ABM1_LS_MIN_PIXEL_VALUE_THRES, 0,
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ABM1_LS_MAX_PIXEL_VALUE_THRES, 1000);
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REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0,
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ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, 1,
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ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, 1,
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ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1);
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}
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static unsigned int dce_abm_get_current_backlight(struct abm *abm)
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{
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struct dce_abm *abm_dce = TO_DCE_ABM(abm);
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unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
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/* return backlight in hardware format which is unsigned 17 bits, with
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* 1 bit integer and 16 bit fractional
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*/
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return backlight;
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}
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static unsigned int dce_abm_get_target_backlight(struct abm *abm)
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{
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struct dce_abm *abm_dce = TO_DCE_ABM(abm);
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unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL);
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/* return backlight in hardware format which is unsigned 17 bits, with
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* 1 bit integer and 16 bit fractional
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*/
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return backlight;
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}
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static bool dce_abm_set_level(struct abm *abm, uint32_t level)
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{
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struct dce_abm *abm_dce = TO_DCE_ABM(abm);
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if (abm->dmcu_is_running == false)
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return true;
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REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
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1, 80000);
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/* setDMCUParam_ABMLevel */
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REG_UPDATE_2(MASTER_COMM_CMD_REG,
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MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET,
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MASTER_COMM_CMD_REG_BYTE2, level);
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/* notifyDMCUMsg */
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REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
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return true;
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}
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static bool dce_abm_immediate_disable(struct abm *abm)
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{
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struct dce_abm *abm_dce = TO_DCE_ABM(abm);
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if (abm->dmcu_is_running == false)
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return true;
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dce_abm_set_pipe(abm, MCP_DISABLE_ABM_IMMEDIATELY);
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abm->stored_backlight_registers.BL_PWM_CNTL =
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REG_READ(BL_PWM_CNTL);
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abm->stored_backlight_registers.BL_PWM_CNTL2 =
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REG_READ(BL_PWM_CNTL2);
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abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
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REG_READ(BL_PWM_PERIOD_CNTL);
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REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
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&abm->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
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return true;
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}
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static bool dce_abm_init_backlight(struct abm *abm)
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{
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struct dce_abm *abm_dce = TO_DCE_ABM(abm);
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uint32_t value;
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/* It must not be 0, so we have to restore them
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* Bios bug w/a - period resets to zero,
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* restoring to cache values which is always correct
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*/
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REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
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if (value == 0 || value == 1) {
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if (abm->stored_backlight_registers.BL_PWM_CNTL != 0) {
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REG_WRITE(BL_PWM_CNTL,
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abm->stored_backlight_registers.BL_PWM_CNTL);
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REG_WRITE(BL_PWM_CNTL2,
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abm->stored_backlight_registers.BL_PWM_CNTL2);
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REG_WRITE(BL_PWM_PERIOD_CNTL,
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abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
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REG_UPDATE(LVTMA_PWRSEQ_REF_DIV,
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BL_PWM_REF_DIV,
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abm->stored_backlight_registers.
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LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
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} else {
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/* TODO: Note: This should not really happen since VBIOS
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* should have initialized PWM registers on boot.
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*/
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REG_WRITE(BL_PWM_CNTL, 0xC000FA00);
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REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
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}
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} else {
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abm->stored_backlight_registers.BL_PWM_CNTL =
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REG_READ(BL_PWM_CNTL);
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abm->stored_backlight_registers.BL_PWM_CNTL2 =
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REG_READ(BL_PWM_CNTL2);
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abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
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REG_READ(BL_PWM_PERIOD_CNTL);
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REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
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&abm->stored_backlight_registers.
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LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
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}
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/* Have driver take backlight control
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* TakeBacklightControl(true)
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*/
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value = REG_READ(BIOS_SCRATCH_2);
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value |= ATOM_S2_VRI_BRIGHT_ENABLE;
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REG_WRITE(BIOS_SCRATCH_2, value);
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/* Enable the backlight output */
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REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
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/* Unlock group 2 backlight registers */
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REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
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BL_PWM_GRP1_REG_LOCK, 0);
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return true;
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}
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static bool dce_abm_set_backlight_level_pwm(
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struct abm *abm,
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unsigned int backlight_pwm_u16_16,
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unsigned int frame_ramp,
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unsigned int controller_id,
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bool use_smooth_brightness)
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{
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struct dce_abm *abm_dce = TO_DCE_ABM(abm);
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DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
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backlight_pwm_u16_16, backlight_pwm_u16_16);
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/* If DMCU is in reset state, DMCU is uninitialized */
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if (use_smooth_brightness)
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dmcu_set_backlight_level(abm_dce,
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backlight_pwm_u16_16,
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frame_ramp,
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controller_id);
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else
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driver_set_backlight_level(abm_dce, backlight_pwm_u16_16);
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return true;
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}
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static const struct abm_funcs dce_funcs = {
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.abm_init = dce_abm_init,
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.set_abm_level = dce_abm_set_level,
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.init_backlight = dce_abm_init_backlight,
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.set_pipe = dce_abm_set_pipe,
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.set_backlight_level_pwm = dce_abm_set_backlight_level_pwm,
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.get_current_backlight = dce_abm_get_current_backlight,
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.get_target_backlight = dce_abm_get_target_backlight,
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.set_abm_immediate_disable = dce_abm_immediate_disable
|
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};
|
|
|
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static void dce_abm_construct(
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struct dce_abm *abm_dce,
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struct dc_context *ctx,
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const struct dce_abm_registers *regs,
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const struct dce_abm_shift *abm_shift,
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const struct dce_abm_mask *abm_mask)
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{
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struct abm *base = &abm_dce->base;
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|
|
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base->ctx = ctx;
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base->funcs = &dce_funcs;
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base->stored_backlight_registers.BL_PWM_CNTL = 0;
|
|
base->stored_backlight_registers.BL_PWM_CNTL2 = 0;
|
|
base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0;
|
|
base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0;
|
|
base->dmcu_is_running = false;
|
|
|
|
abm_dce->regs = regs;
|
|
abm_dce->abm_shift = abm_shift;
|
|
abm_dce->abm_mask = abm_mask;
|
|
}
|
|
|
|
struct abm *dce_abm_create(
|
|
struct dc_context *ctx,
|
|
const struct dce_abm_registers *regs,
|
|
const struct dce_abm_shift *abm_shift,
|
|
const struct dce_abm_mask *abm_mask)
|
|
{
|
|
struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
|
|
|
|
if (abm_dce == NULL) {
|
|
BREAK_TO_DEBUGGER();
|
|
return NULL;
|
|
}
|
|
|
|
dce_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask);
|
|
|
|
abm_dce->base.funcs = &dce_funcs;
|
|
|
|
return &abm_dce->base;
|
|
}
|
|
|
|
void dce_abm_destroy(struct abm **abm)
|
|
{
|
|
struct dce_abm *abm_dce = TO_DCE_ABM(*abm);
|
|
|
|
kfree(abm_dce);
|
|
*abm = NULL;
|
|
}
|